1 | /* ################## Ethernet peripheral configuration ##################### */
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2 |
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3 | /* Section 1 : Ethernet peripheral configuration */
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4 |
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5 | /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
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6 | #define MAC_ADDR0 2
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7 | #define MAC_ADDR1 0
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8 | #define MAC_ADDR2 0
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9 | #define MAC_ADDR3 0
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10 | #define MAC_ADDR4 0
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11 | #define MAC_ADDR5 0
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12 |
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13 | /* Definition of the Ethernet driver buffers size and count */
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14 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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15 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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16 | #define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
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17 | #define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
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18 |
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19 | /* Section 2: PHY configuration section */
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20 |
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21 | /* DP83848 PHY Address*/
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22 | #define DP83848_PHY_ADDRESS 0x01
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23 | /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
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24 | #define PHY_RESET_DELAY ((uint32_t)0x000000FF)
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25 | /* PHY Configuration delay */
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26 | #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
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27 |
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28 | #define PHY_READ_TO ((uint32_t)0x0000FFFF)
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29 | #define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
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30 |
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31 | /* Section 3: Common PHY Registers */
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32 |
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33 | #define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
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34 | #define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
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35 |
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36 | #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
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37 | #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
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38 | #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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39 | #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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40 | #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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41 | #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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42 | #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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43 | #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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44 | #define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
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45 | #define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
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46 |
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47 | #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
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48 | #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
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49 | #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
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50 |
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51 | /* Section 4: Extended PHY Registers */
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52 |
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53 | //#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
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54 | #define PHY_SR ((uint16_t)31) /*!< PHY status register Offset */ // Andre
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55 | #define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
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56 | #define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
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57 |
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58 | #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
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59 | #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
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60 | #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
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61 |
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62 | #define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
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63 | #define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
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64 |
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65 | #define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
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66 | #define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
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