1  | //////////////////////////////////////////  TWI_M_start  //////////////////////////////////////////
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2  |   
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3  |   /*
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4  |    starting TWI with slave's address and choosing mode between MT and MR
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5  | 
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6  |    read_or_write=1: MR      read_or_write=0: MT    option is for first sending (initialization)
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7  |    
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8  |    returns TWI_M_START_FAILED_1, TWI_M_START_FAILED_2 or START_SUCCEED
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9  |   */
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10  |   int8_t TWI_M_start(uint8_t address, uint8_t read_or_write, uint8_t option)
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11  |   {
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12  |     
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13  |     TWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN); // enable interrupt flag, send start, enable TWI
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14  |     
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15  |       while( ! ( TWCR & (1 << TWINT) ) ); // wait for operation 
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16  |       
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17  |         if( ( (TW_STATUS) != M_START ) && ( (TW_STATUS) != M_REPEADED_START ) ) // checking error
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18  |         {
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19  |           
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20  |           TWI_M_stop();
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21  |           return TWI_M_START_FAILED_1;  // return error
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22  |           
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23  |         }
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24  |     
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25  |     TWDR =  ( (address << 1) + read_or_write) | option; // choosing slave showing if MR or MT mode starts
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26  |     //TWDR = (address) + read_or_write; // choosing slave showing if MR or MT mode starts
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27  |     TWCR = (1 << TWINT) | (1 << TWEN); // TWINT bit has to be set for transmission  
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28  |     
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29  |       while( ! ( TWCR & (1 << TWINT) ) ); // wait for operation 
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30  |       
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31  |         //if( ( (TW_STATUS & 0b11111000) != MT_SLA_W_TRANS_ACK_REC ) && ( (TW_STATUS & 0b11111000) != MR_SLA_R_TRANS_ACK_REC ) ) // checking error // TWSR // 0x18 // 0x40
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32  |         if( ( (TW_STATUS) != MT_SLA_W_TRANS_ACK_REC ) && ( (TW_STATUS) != MR_SLA_R_TRANS_ACK_REC ) )
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33  |         {
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34  |         
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35  |           TWI_M_stop();
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36  |           return TWI_M_START_FAILED_2;
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37  |         
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38  |         }
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39  | 
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40  |     return START_SUCCEED;
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41  |   
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42  |   }
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43  | 
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44  | //$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
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45  | 
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46  | 
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47  | //////////////////////////////////////////  TWI_M_write  //////////////////////////////////////////
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48  |   
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49  |   /*
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50  |    writes in TWI data register
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51  |    
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52  |    returns MT_DATA_TRAMS_FAILED or MT_DATA_TRANS_SUCCEED
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53  |   */
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54  |   int8_t TWI_M_write(uint8_t data)
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55  |   {
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56  |         
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57  |     TWDR = data; // send data
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58  |     
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59  |     TWCR = (1 << TWINT) | (1 << TWEN); // TWINT bit has to be set for transmission
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60  |     
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61  |       while( ! ( TWCR & (1 << TWINT) ) ); // wait for operation
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62  |     
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63  |         if( ( (TW_STATUS) != MT_DATA_TRANS_ACK_RETURN ) && ( (TW_STATUS) != MT_DATA_TRANS_NACK_RETURN ) ) // checking error
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64  |         {
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65  |           
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66  |           TWI_M_stop();      
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67  |           return MT_DATA_TRANS_FAILED;    
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68  |               
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69  |         }
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70  | 
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71  |     return MT_DATA_TRANS_SUCCEED;
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72  |   
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73  |   }
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74  | 
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75  | //$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
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76  | 
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77  | 
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78  | 
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79  | 
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80  | 
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81  | //////////////////////////////////////////  TWI_M_stop  //////////////////////////////////////////
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82  |   
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83  |   /*
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84  |    stops TWI
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85  |    
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86  |    no return
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87  |   */
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88  |   void TWI_M_stop()
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89  |   {
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90  |     
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91  |     TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);
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92  |   
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93  |   }
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94  | 
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95  | //$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
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