STM32f103TB PWM auf Timer 2 läuft nicht.

[Jan K. (jan_k)]

Hi Leute,

bin etwas verwirrt, ich möchte einen einfachen PWM Ausgang mit Timer 2 
am Port PA1 auf einem STM32F103TB VFQFPN36 realisieren. Laut Datenblatt 
ist TIM2 _CH2 auf PA1 gemappt.
Problem: Am Ausgang tut sich nix.

Ich stelle jetzt nur die gekürzten Versionen der Timer und GPIO Inits 
rein, vielleicht fällt direkt etwas auf. Sonst mache ich eine 
abgespeckte kompilierbare Version.

Der Timer1 funktioniert wie gewünscht, ebenso springt der Controller in 
die ISR vom Timer 2.

/* ... header .... */


// masks for setting GPIO bits
#define OUT_PP_MASK     ((uint32_t)( (0x01 << 1 | 0x01) | 0x00 << 2) )
#define IN_ANALOG_MASK    ((uint32_t)(0x00 | 0x00 << 2) )
#define IN_FLOAT_MASK      ((uint32_t)(0x00 | 0x01 << 2) )
#define OUT_ALT_PP_MASK    ((uint32_t)( ( 0x01 << 1 | 0x01 ) | ((0x01 << 1 | 0x00) << 2) ) )

#define CORE_CLOCK ((uint32_t) 64000000)


void PCBA_Configuration( void ) // wird vor dem main loop aufgerufen
{
  ConfigureGPIO();
  ConfigureTimer();
  ConfigurePWM();
}

void ConfigureGPIO( void )
{
  RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; // clock port a
  RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; // clock port b
  RCC->APB2ENR |= RCC_APB2ENR_AFIOEN; // enable alternative function clock

  GPIOA->CRL = ( GPIOA->CRL & 0x00000000 )  // each half byte for mode and config for each Port. 0x00 = reset state there. here: alter every port
               | ( IN_ANALOG_MASK << 4 * 0 | OUT_ALT_PP_MASK << 4 * 1 | OUT_ALT_PP_MASK << 4 * 2 | IN_FLOAT_MASK << 4 * 3
                   | IN_ANALOG_MASK << 4 * 4 | IN_ANALOG_MASK << 4 * 5 | OUT_PP_MASK << 4 * 6 | OUT_PP_MASK << 4 * 7 );

  GPIOB->CRL = ( GPIOB->CRL & 0x00FFFFF0 )// only alter pb0, pb6, pb7
               | ( OUT_PP_MASK << 4 * 0 | OUT_ALT_PP_MASK << 4 * 6 | IN_FLOAT_MASK << 4 * 7 ) ;

  // debug pins: pa2, pa3
  GPIOA->CRL = ( GPIOA->CRL & 0xFFFF00FF )   //
               | ( OUT_PP_MASK << 4 * 2 | OUT_PP_MASK << 4 * 3 ) ;
  //GPIOA->BRR = GPIO_Pin_2 | GPIO_Pin_3;

  AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1; // trace on
}


void ConfigurePWM( void )
{
  // output pins are defined in ConfigureGPIO!

  /* -----------------------------------------------------------------------
    Time base configuration
    TIM2CLK = APB1clk = CORE_CLOCK/2 = 32MHz usually, TIM2 counter clock frequency = TIM2CLK/(PSC + 1) = 100Hz => APB1ck / (TimSollClock*ARR) - 1 = PSC
    TIM2 ARR Register; TIM1 Frequency = TIM1 counter clock frequency/(ARR+1) = x kHz.
    TIM2 Frequency = 100 Hz.
    TIM2 Channel2 duty cycle = (TIM2_CCR2/ TIM2_ARR) * 100 = 50%
  ----------------------------------------------------------------------- */

  #define ARR_VAL ((uint16_t)4000)
  #define PWM_FREQ ((uint16_t)100)

  RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;       // enable clock for TIM2

  TIM2->PSC = ( uint16_t )( ( CORE_CLOCK / ( 2 * PWM_FREQ * ARR_VAL ) ) - ( uint32_t )1 );   // 800 kHz counter @ 32 MHz
  TIM2->ARR = ARR_VAL - 1;

  TIM2->CCR2  = ARR_VAL / 2;                                            // set channel 2 duty cycle
  TIM2->CCMR1 = TIM_CCMR1_OC2M | TIM_CCMR1_OC2PE;         // set channel 2 PWM mode 2, pre load enabled.

  TIM2->CCER = TIM_CCER_CC2E;    // enable capture and compare, active high
  TIM2->CR1 = TIM_CR1_ARPE | TIM_CR1_URS;            // downcounter, arr preload active, only over/underflow generate interrupt
  TIM2->DIER = TIM_DIER_UIE;                          // Enable Update event interrupt
  NVIC_SetPriority( TIM2_IRQn, 0 );                                               // set interrupt priority TIM2
  NVIC_EnableIRQ( TIM2_IRQn );                                                        // enable TIM2 interrupts

  TIM2->EGR |= TIM_EGR_UG; // generate update event
  TIM2->CR1 |= TIM_CR1_CEN; // start
}

void SetPWMOut( float fValue )
{
  float dc, ccr;
  dc = .028125 * fValue + .5; // 95% = +16mm, 5% = -16mm, 50% = 0mm
  ccr = dc * ARR_VAL;
  TIM2->CCR2 = ( uint16_t )ccr;
}

void TIM2_IRQHandler( void )
{
  if ( TIM2->SR & 0x01 )
  {
    TIM2->SR &= ~TIM_IT_Update;
  }
}

void ConfigureTimer( void )
{
  RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;                     // enable clock for TIM1
  /* -----------------------------------------------------------------------
    Time base configuration
    TIM1CLK = APB2 clock = 64 MHz,  TIM1 counter clock frequency = TIM1CLK/(PSC + 1) = 20 kHz => APB2ck / TimSollClock*ARR - 1 = PSC
    TIM1 ARR Register = 4 => TIM1 Frequency = TIM1 counter clock frequency/(ARR+1) = 5 kHz.
  ----------------------------------------------------------------------- */
  TIM1->PSC = CORE_CLOCK / 20e3 - 1;                             // set prescaler
  TIM1->ARR = 4 - 1;                                  // set auto-reload

  TIM1->CCR1  = 0x0000;                           //
  TIM1->CCR2  = 0x7D00;                           //
  TIM1->CCR3  = 0x0000;                           //
  TIM1->CCR4  = 0x0000;                           //
  TIM1->CCMR1 = 0x0100;                           //
  TIM1->CCMR2 = 0x0000;                           //
  TIM1->CCER  = 0x0000;                           // set capture/compare enable register
  TIM1->SMCR  = 0x0000;                           // set slave mode control register

  TIM1->CR1 = 0x0000 & 0xFFFE;                    // set command register 1
  TIM1->CR2 = 0x0010;                             // set command register 2

  TIM1->DIER = 0x0001;                            // enable interrupt

  NVIC_EnableIRQ( TIM1_UP_IRQn );
  NVIC_SetPriority( TIM1_UP_IRQn, 1 );
}

Vielen Dank fürs drüber gucken!