1 | void MC_init(){
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2 |
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3 | /*PM initializations*/
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4 | PM_CPUMASK |= PM_CPUMASK_OCDEN; // OnChipDebugger
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5 | PM_PBAMASK |= PM_PBAMASK_ENS; // enabling interrupt, gpio and pwm clocks, to be sure (should be enabled by default/reset)
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6 |
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7 | /*interrupt controller initializations*/
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8 |
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9 | IPR12_PWM &= IPR_LEVEL0; //zeroing
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10 | IPR12_PWM |= IPR_LEVEL1;
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11 |
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12 |
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13 | /*PWM channels initializations*/
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14 |
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15 | PWM_MR |= PWM_DEFCLK; //Mode Register, DEFCLK => selcted by prea, preb
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16 |
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17 | //assigning unmanipulated clock to the channels (value = 0)
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18 | PWM_CMR0 &= PWM_CMR_STDCLK;
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19 | PWM_CMR1 &= PWM_CMR_STDCLK;
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20 | PWM_CMR2 &= PWM_CMR_STDCLK;
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21 | PWM_CMR3 &= PWM_CMR_STDCLK;
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22 | PWM_CMR4 &= PWM_CMR_STDCLK;
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23 | PWM_CMR5 &= PWM_CMR_STDCLK;
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24 | PWM_CMR6 &= PWM_CMR_STDCLK;
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25 |
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26 | //assigning polarity to start on lowlevel on all channels (value = 0)
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27 | PWM_CMR0 &= PWM_CMR_POL_L;
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28 | PWM_CMR1 &= PWM_CMR_POL_L;
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29 | PWM_CMR2 &= PWM_CMR_POL_L;
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30 | PWM_CMR3 &= PWM_CMR_POL_L;
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31 | PWM_CMR4 &= PWM_CMR_POL_L;
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32 | PWM_CMR5 &= PWM_CMR_POL_L;
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33 | PWM_CMR6 &= PWM_CMR_POL_L;
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34 |
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35 | //assigning left alignment to all channels (value = 0)
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36 | PWM_CMR0 &= PWM_CMR_ALG_L;
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37 | PWM_CMR1 &= PWM_CMR_ALG_L;
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38 | PWM_CMR2 &= PWM_CMR_ALG_L;
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39 | PWM_CMR3 &= PWM_CMR_ALG_L;
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40 | PWM_CMR4 &= PWM_CMR_ALG_L;
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41 | PWM_CMR5 &= PWM_CMR_ALG_L;
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42 | PWM_CMR6 &= PWM_CMR_ALG_L;
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43 |
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44 | //assigning period of 1024 to all channels
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45 | PWM_CPRD0 |= PWM_DEFPRD;
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46 | PWM_CPRD1 |= PWM_DEFPRD;
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47 | PWM_CPRD2 |= PWM_DEFPRD;
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48 | PWM_CPRD3 |= PWM_DEFPRD;
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49 | PWM_CPRD4 |= PWM_DEFPRD;
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50 | PWM_CPRD5 |= PWM_DEFPRD;
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51 | PWM_CPRD6 |= PWM_DEFPRD;
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52 |
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53 | //assigning individual duty cycles to the channels
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54 | PWM_CDTY0 |= 0x100; //3,3V *1/4 = 0,825V
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55 | PWM_CDTY1 |= 0x200; //3,3V *1/2 = 1,65V
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56 | PWM_CDTY2 |= 0x050; //3,3V *1/8 = 0,4125V
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57 | PWM_CDTY3 |= 0x020; //3,3V *1/20= 0,165V
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58 | PWM_CDTY4 |= 0x010; //3,3V *1/40= 0,0825V
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59 | PWM_CDTY5 |= 0x300; //3,3V *3/4 = 2,475V
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60 | PWM_CDTY6 |= 0x350; //3,3V *7/8 = 2,8875V
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61 |
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62 |
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63 | /*GPIO initializations*/
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64 | GPIO_GPER &= PWM_PERIPHERAL_ENABLE; //resulting: FFBA9E7F
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65 | GPIO_PMR0 |= PMR0_PWM_BITS; //MUX Bit 0
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66 | GPIO_PMR1 |= PMR1_PWM_BITS; //MUX Bit 1
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67 |
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68 |
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69 | PWM_IER |= PWM_IER_ALL; // enable interrupt for all channels
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70 | PWM_ENA |= PWM_ENA_ALL; // enable PWM channels
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71 |
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72 | }
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