FPGA / Daten Multiplexen

library ieee;

use ieee.std_logic_1164.all;

entity mux is

    port (

        channel_1_in : in   std_logic;

        channel_2_in : in   std_logic;

        channel_3_in : in   std_logic;

        channel_4_in : in   std_logic;

        --

        sel          : in   std_logic_vector(1 downto 0);

        channel_out  : out  std_logic;

    );

end entity mux;

architecture rtl of mux is

begin

    channel_out <= channel_1_in when sel = "00" else

                   channel_2_in when sel = "01" else

                   channel_3_in when sel = "10" else

                   channel_4_in;

end architecture rtl;