1 | volatile uint16_t sendbuffer[128];
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2 |
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3 |
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4 |
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5 |
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6 | void init_dma()
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7 | {
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8 | static TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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9 | static DMA_InitTypeDef DMA_InitStructure;
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10 | static NVIC_InitTypeDef NVIC_InitStructure;
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11 |
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12 | RCC_PCLK1Config(RCC_HCLK_Div1);
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13 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
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14 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
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15 |
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16 |
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17 | //Clear Flags
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18 | DMA_ClearFlag(DMA2_Stream5, DMA_FLAG_FEIF5 | DMA_FLAG_DMEIF5 | DMA_FLAG_TEIF5 | DMA_FLAG_HTIF5 | DMA_FLAG_TCIF5);
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19 |
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20 | // DMA2 disable
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21 | DMA_Cmd(DMA2_Stream5, DISABLE);
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22 |
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23 | DMA_DeInit(DMA2_Stream5);
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24 |
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25 | DMA_InitStructure.DMA_Channel = DMA_Channel_6; // Stream 5 Channel 6 is TIM1_TRIG
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26 | DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&GPIOD->ODR;
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27 | DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0;
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28 | DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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29 | DMA_InitStructure.DMA_BufferSize = 128;
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30 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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31 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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32 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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33 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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34 | DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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35 | DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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36 | DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
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37 | DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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38 | DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_INC16;
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39 | DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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40 | DMA_Init(DMA2_Stream5, &DMA_InitStructure);
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41 |
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42 | DMA_FlowControllerConfig(DMA2_Stream5, DMA_FlowCtrl_Memory);
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43 |
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44 | // Timebase
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45 | TIM_TimeBaseStructure.TIM_Period = 1;
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46 | TIM_TimeBaseStructure.TIM_Prescaler = 0;
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47 | TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
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48 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Down;
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49 | TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
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50 | TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
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51 | TIM_Cmd(TIM1, ENABLE);
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52 |
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53 | // Set and enable interrupt
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54 | TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
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55 |
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56 | // set and enable interrupt
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57 | DMA_ITConfig(DMA2_Stream5, DMA_IT_TC, ENABLE);
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58 |
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59 | NVIC_InitStructure.NVIC_IRQChannel = DMA2_Stream5_IRQn;
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60 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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61 | NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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62 | NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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63 | NVIC_Init(&NVIC_InitStructure);
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64 | }
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65 |
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66 | void start_dma()
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67 | {
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68 | DMA2_Stream5->M0AR = (uint32_t)&sendbuffer;
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69 | DMA2->LIFCR = 0b111101;
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70 | DMA2_Stream5->CR |= DMA_SxCR_EN;
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71 | DMA_Cmd(DMA2_Stream5, ENABLE);
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72 | }
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73 |
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74 | //----------------------------------------------------------------------------
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75 | void DMA2_Stream5_IRQHandler()
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76 | {
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77 | DMA2->HIFCR = DMA_HIFCR_CTCIF5;
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78 |
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79 | GPIOA->BSRRL = GPIO_Pin_9; // LED ON -> High Pegel
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80 | return;
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81 | }
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