Gast
#296777
Hi
Bin vhdl anfänger und will auf einem vga monitor daten anzeigen. dazu
mach ich ein "array (0 to 639,0 to 489) of std_logic_vector (1 DOWNTO
0)" ich kann es aber nicht syntesieren. ich benuetze mentorgrafics
Precision auf einem spartan 2. bin um jede hilfe dankbar.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY ram_sym IS
PORT(
sys_clk : IN std_logic;
reset : IN std_logic;
l_avarage : IN std_logic_vector (8 DOWNTO 0);
l_colume : IN std_logic_vector (8 DOWNTO 0);
l_new_data_clk : IN std_logic;
r_avarage : IN std_logic_vector (8 DOWNTO 0);
r_colume : IN std_logic_vector (8 DOWNTO 0);
r_new_data_clk : IN std_logic;
colum : IN std_logic_vector ( 9 DOWNTO 0 );
line : IN std_logic_vector ( 8 DOWNTO 0 );
pixel : OUT std_logic_vector ( 1 DOWNTO 0 )
);
-- Declarations
END ram_sym ;
--
ARCHITECTURE behav OF ram_sym IS
type MEMORY is array (0 to 639,0 to 489) of std_logic_vector (1
DOWNTO 0);
--column , line
Signal colum_ram: MEMORY;
Signal colour: std_logic_vector (1 DOWNTO 0);
BEGIN
colour<="01";
process(sys_clk,reset)
begin
if(reset='0') then
for line_ctr in 0 to 489 loop
for columne_ctr in 0 to 639 loop
colum_ram(conv_integer(columne_ctr),conv_integer(line_ctr))<="00";
end loop;
end loop;
elsif (sys_clk = '1'and sys_clk'event)then
colum_ram(conv_integer(l_colume),conv_integer(l_avarage(8
downto 1)))<=colour;
colum_ram(conv_integer(r_colume),(conv_integer(r_avarage(8
downto 1))+233))<=colour;
pixel<=colum_ram(conv_integer(colum),conv_integer(line));
else
end if;
end process;
END ARCHITECTURE behav;