1 | void User_Init_Timer1(uint8_t Presc, uint8_t period, uint16_t PulseN){
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2 |
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3 | /* Configure register bits for Channel 1*/
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4 | TIM1->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1M; /* Reset bits of OC1M register*/
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5 | TIM1->CCER |= TIM_CCER_CC1E; /* Enable the Compare output channel 1 */
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6 | TIM1->CCMR1 &= (uint16_t)~TIM_CCMR1_CC1S; /* Set CC1 as output */
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7 | TIM1->CCMR1 |= TIM_OCMODE_PWM2; /* OC1 is high until CCR1 */
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8 | TIM1->CCER &= (uint16_t)~TIM_CCER_CC1P; /* Reset CC1P register */
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9 | TIM1->CCR1 = period/2; /* Set the compare value channel 1*/
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10 |
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11 |
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12 | /* Configure register bits for Channel 2*/
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13 | TIM1->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2M; /* Reset bits of OC2M register*/
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14 | TIM1->CCER |= TIM_CCER_CC2E; /* Enable the Compare output channel 2 */
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15 | TIM1->CCMR1 &= (uint16_t)~TIM_CCMR1_CC2S; /* Set CC2 as output */
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16 | TIM1->CCMR1 |= TIM_OCMODE_PWM2_CH2; /* OC2 is high until CCR2 */
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17 | TIM1->CCER &= (uint16_t)~TIM_CCER_CC2P; /* Reset CC2P register */
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18 | TIM1->CCR2 = period/2; /* Set the compare value channel 2*/
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19 |
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20 |
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21 | /* Configure register bits for Channel 3*/
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22 | TIM1->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3M; /* Reset bits of OC3M register*/
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23 | TIM1->CCER |= TIM_CCER_CC3E; /* Enable the Compare output channel 3 */
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24 | TIM1->CCMR2 &= (uint16_t)~TIM_CCMR2_CC3S; /* Set CC3 as output */
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25 | TIM1->CCMR2 |= TIM_OCMODE_PWM2_CH3; /* OC2 is high until CCR2 */
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26 | TIM1->CCER &= (uint16_t)~TIM_CCER_CC3P; /* Reset CC3P register */
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27 | TIM1->CCR3 = period/2; /* Set the compare value channel 3*/
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28 |
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29 | /* Configure register bits for Channel 4*/
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30 | TIM1->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4M; /* Reset bits of OC4M register*/
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31 | TIM1->CCER |= TIM_CCER_CC4E; /* Enable the Compare output channel 4 */
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32 | TIM1->CCMR2 &= (uint16_t)~TIM_CCMR2_CC4S; /* Set CC4 as output */
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33 | TIM1->CCMR2 |= TIM_OCMODE_PWM2_CH4; /* OC2 is high until CCR2 */
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34 | TIM1->CCER &= (uint16_t)~TIM_CCER_CC4P; /* Reset CC4P register */
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35 | TIM1->CCR4 = period/2; /* Set the compare value channel 4*/
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36 |
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37 | /* General configuration for all Timer 1 Channels 1-4*/
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38 | RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; /* Peripheral clock enable */
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39 | TIM1->CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); /* Reset bits of CMS (Edge-aligned mode) and DIR generally */
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40 | TIM1->CR1 |= TIM_COUNTERMODE_UP; /* Select the up counter mode */
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41 | TIM1->CR1 &= ~TIM_CR1_CKD; /* Erase bits of CKD */
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42 | TIM1->CR1 |= TIM_CLOCKDIVISION_DIV1; /* Set the clock division to 1*/
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43 | TIM1->PSC = Presc; /* Set the Prescaler value */
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44 | TIM1->ARR = period - 1; /* Set the Auto-reload value*/
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45 | TIM1->RCR = PulseN - 1; /* Set the repetition counter value*/
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46 | TIM1->EGR = TIM_EGR_UG; /* Generate an update event to reload Prescaler and Repetition counter value immediately*/
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47 | TIM1->CR1 |= TIM_CR1_OPM; /* Activate the one pulse mode*/
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48 | TIM1->CCER |= TIM_OCPOLARITY_HIGH; /* Set the Output Compare Polarity to High */
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49 | TIM1->SMCR = RESET; /* Configure the Internal Clock Source*/
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50 | TIM1->BDTR |= TIM_BDTR_MOE; /* Enable the TIM main Output */
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51 |
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52 | }
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