MSP430: Timer Register TAxIV

[Daniel (Gast)]

Hallo,

bei den Timern bin ich auf das Register TAxIV gestoßen, verstehe aber 
dessen Funktion nicht.

Im Reference Manual wird es wie folgt beschrieben:

Timer_A Interrupts
Two interrupt vectors are associated with the 16-bit Timer_A module:
• TAxCCR0 interrupt vector for TAxCCR0 CCIFG
• TAxIV interrupt vector for all other CCIFG flags and TAIFG
In capture mode, any CCIFG flag is set when a timer value is captured in 
the associated TAxCCRn
register. In compare mode, any CCIFG flag is set if TAxR counts to the 
associated TAxCCRn value.
Software may also set or clear any CCIFG flag. All CCIFG flags request 
an interrupt when their
corresponding CCIE bit and the GIE bit are set.

TAxCCR0 Interrupt
The TAxCCR0 CCIFG flag has the highest Timer_A interrupt priority and 
has a dedicated interrupt vector
as shown in Figure 17-15. The TAxCCR0 CCIFG flag is automatically reset 
when the TAxCCR0 interrupt
request is serviced.

TAxIV, Interrupt Vector Generator
The TAxCCRy CCIFG flags and TAIFG flags are prioritized and combined to 
source a single interrupt
vector. The interrupt vector register TAxIV is used to determine which 
flag requested an interrupt.
The highest-priority enabled interrupt generates a number in the TAxIV 
register (see register description).
This number can be evaluated or added to the program counter to 
automatically enter the appropriate
software routine. Disabled Timer_A interrupts do not affect the TAxIV 
value.
Any access, read or write, of the TAxIV register automatically resets 
the highest-pending interrupt flag. If
another interrupt flag is set, another interrupt is immediately 
generated after servicing the initial interrupt.
For example, if the TAxCCR1 and TAxCCR2 CCIFG flags are set when the 
interrupt service routine
accesses the TAxIV register, TAxCCR1 CCIFG is reset automatically. After 
the RETI instruction of the
interrupt service routine is executed, the TAxCCR2 CCIFG flag generates 
another interrupt.

2Eh TAxIV Timer_Ax Interrupt Vector Read only Word 0000h

Timer_A interrupt vector value
00h = No interrupt pending
02h = Interrupt Source: Capture/compare 1; Interrupt Flag: TAxCCR1 
CCIFG; Interrupt Priority: Highest
04h = Interrupt Source: Capture/compare 2; Interrupt Flag: TAxCCR2 CCIFG
06h = Interrupt Source: Capture/compare 3; Interrupt Flag: TAxCCR3 CCIFG
08h = Interrupt Source: Capture/compare 4; Interrupt Flag: TAxCCR4 CCIFG
0Ah = Interrupt Source: Capture/compare 5; Interrupt Flag: TAxCCR5 CCIFG
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG
0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; 
Interrupt Priority: Lowest


Kann mit jemand weiterhelfen? Dank!

[Rufus Τ. F. (rufus)]

Das Register dient dazu, im Timer_A-Interrupthandler herauszufinden, was 
genau den Interrupt ausgelöst hat.

> The interrupt vector register TAxIV is used to determine
> which flag requested an interrupt.

Wenn Du Dir die Codebeispiele ansiehst, die TI für Deinen (ungenannten) 
MSP430 herausgegeben hat, wirst Du dort auch Beispiele für den Gebrauch 
der unterschiedlichen Timerinterruptquellen finden.

[Daniel (Gast)]

Das habe ich auch so vermutet gehabt, jedoch bekomme keine gesetzten 
Bits während eines Interrupts.

  TA0CTL = TASSEL__SMCLK + TACLR + ID_1;
  TA0CCTL0 = CCIE   ;          
  TA0CCR0 = 50000;              
  TA0EX0 = TAIDEX_5;
  TA0CTL |= MC__UP;            
  
  __enable_interrupt();


#pragma vector=TIMER0_A0_VECTOR
__interrupt void Timer4(void){
  ;
}

Der Interrupt wird aufgerufen.

[Daniel (Gast)]

Ahhhh, eine kleine Ergänzung:

Da ich nur CCR0 nehme, dessen Interrupt nicht von TAxIV behandelt wird, 
kann auch kein Bit gesetzt werden, aber Danke dir nochmals (hatte ich 
eben vergessen -.- )