GHDL --STD=08 elaborate klappt nicht

library STD;                            -- you don't need STD, it is automatic

library IEEE;                           -- but may need other libraries

use IEEE.std_logic_1164.all;            -- basic logic types

use STD.textio.all;                     -- basic I/O

use IEEE.std_logic_textio.all;          -- I/O for logic types

entity hello_world is 

end entity hello_world;

architecture test of hello_world is -- where declarations are placed

  subtype word_32 is std_logic_vector(31 downto 0);  -- simple name

  signal four_32 : word_32 := x"00000AB4";           -- just four in hex

  signal I : integer := 0;  

begin

  my_print : process is                  -- a process is parallel

               variable my_line : line;  -- type 'line' comes from textio

             begin

             L1: for I in 2 to 5 loop

               write(my_line, string'("Hello World 1"));   -- formatting

               writeline(output, my_line);               -- write to "output"

               write(my_line, string'("four_32 = "));   

               hwrite(my_line, four_32); -- format type std_logic_vector as hex

               write(my_line, string'("  I= ")); write(my_line, I);  -- format 'counter' as integer

               wait for 10 ns ;

               write(my_line, string'(" at time ")); write(my_line, now);                     -- format time

               writeline(output, my_line);              -- write to display

             end loop L1;

               wait;

             end process my_print;

end architecture test;

ghdl -a --std=08  *.vhd

ghdl -e hello_world