1 | #include "stm32f1xx.h"
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2 |
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3 |
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4 | void RTC_Handler(void)
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5 | {
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6 | // Toggle LED at PA5
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7 | GPIOA->ODR ^= GPIO_ODR_ODR5;
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8 |
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9 | // Clear interrupt flag
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10 | CLEAR_BIT(RTC->CRL,RTC_CRL_SECF);
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11 | }
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12 |
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13 |
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14 | void initRtc()
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15 | {
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16 | // Enable the backup domain
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17 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN + RCC_APB1ENR_PWREN);
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18 |
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19 | // Enable write access to the backup domain
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20 | SET_BIT(PWR->CR, PWR_CR_DBP);
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21 |
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22 | // Enable LSE oscillator
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23 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
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24 |
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25 | // Wait until LSE oscillator is ready
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26 | while(!READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY)) {}
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27 |
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28 | // Select LSE as clock source for the RTC
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29 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, RCC_BDCR_RTCSEL_LSE);
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30 |
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31 | // Enable the RTC
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32 | SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
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33 |
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34 | // Wait until RTC is synchronized
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35 | while(!READ_BIT(RTC->CRL, RTC_CRL_RSF)) {}
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36 |
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37 | // Wait until last write operation is done
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38 | while(!READ_BIT(RTC->CRL, RTC_CRL_RTOFF)) {}
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39 |
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40 | // Enable second interrupt
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41 | SET_BIT(RTC->CRH,RTC_CRH_SECIE);
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42 |
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43 | // Wait until last write operation is done
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44 | while(!READ_BIT(RTC->CRL, RTC_CRL_RTOFF)) {}
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45 |
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46 | // Enter configuration mode
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47 | SET_BIT(RTC->CRL,RTC_CRL_CNF);
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48 |
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49 | // Divide oscillator frequency by 32767+1 to get seconds
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50 | RTC->PRLL=32767;
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51 | RTC->PRLH=0;
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52 |
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53 | // Leave configuration mode
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54 | CLEAR_BIT(RTC->CRL,RTC_CRL_CNF);
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55 |
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56 | // Wait until last write operation is done
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57 | while(!READ_BIT(RTC->CRL, RTC_CRL_RTOFF)) {}
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58 |
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59 | // Enable interrupt in NVIC
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60 | NVIC_EnableIRQ(3);
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61 | __enable_irq();
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62 | }
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63 |
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64 |
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65 | void initIo()
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66 | {
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67 |
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68 | // Enable Port A
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69 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);
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70 |
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71 | // PA5 = Output
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72 | MODIFY_REG(GPIOA->CRL, GPIO_CRL_CNF5 + GPIO_CRL_MODE5, GPIO_CRL_MODE5_0);
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73 | }
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74 |
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75 |
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76 | int main(void)
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77 | {
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78 | initIo();
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79 | initRtc();
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80 |
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81 | while(1){};
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82 | }
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