Verilog: Initialisierung Vector Array

module jdoodle;

/*

    localparam t[5] = {

        32'hffffffff,

        32'h55555555,

        32'h22222222,

        32'heeeeeeee,

        32'h11111111

    };

  */

  parameter reg [7:0] t [0 : 7]   = '{8'd9, 8'd5, 8'd3, 8'h21, 8'd9, 8'd9, 8'd5, 8'd9};

    initial begin

        #1 Vector = 32'hC5B2B856;

        $monitor("%t,%h,%h,%h,%h,%h,%h,%h,%h",$time,t [0],t [1],t [2],t [3], t[4], t[5], t[6], t[7]);

        #10 $finish;

    end

endmodule

jdoodle.v:11: syntax error

jdoodle.v:11: error: syntax error in parameter list.