XMC4500 mit UART DMA

[Felix (Gast)]

Hallo,

Ich benutze das XMC4500 Relax Kit inkl. XMC-Lib und versuche seit Tagen 
folgendes umzusetzen:
4 UART TX Outputs, welche mit Hilfe von DMA jeweils ein eigenes uint8_t 
Array parallel, also gleichzeitig senden.

Nach Vertiefen ins Datenblatt, sowie in die USIC und DMA Kapitel, kam 
ich zu folgendem Ansatz:

U0C0 für TX1 Output,
U0C1 für TX2 Output,
U1C0 für TX3 Output,
U1C1 für TX4 Output

Soweit so gut. Gleichzeitiges Sender der Arraybuffer unter Verwendung 
von nur TX1 und TX3 funktioniert wunderbar, ebenfalls von TX2 und TX4. 
Bei Verwendung von allen 4 TX, bzw. TX1 & TX2 oder TX3 & TX4, gibt es 
einen "Streit" zwischen den Channels des betreffenden USIC Moduls.

Meine Frage lautet nun: Kann das überhaupt so funktionieren wie ich es 
versuche, oder können beide Channels eines USIC Moduls nicht 
gleichzeitig?

Code reiche ich gerne bei Bedarf nach.

Vielen Dank,
Felix

[Felix (Gast)]

Alle 4 Arrays sind mit gleichen Daten gefüllt. Mit einer durchgehenden 
Zahlenfolge von 0 bis 99.

Mein Code:

#define BUFFER_LENGTH 100

volatile uint8_t DMXBufferU0C0[BUFFER_LENGTH];
volatile uint8_t DMXBufferU0C1[BUFFER_LENGTH];
volatile uint8_t DMXBufferU1C0[BUFFER_LENGTH];
volatile uint8_t DMXBufferU1C1[BUFFER_LENGTH];

static XMC_UART_CH_CONFIG_t uart_config =
{
  .baudrate = 250000U,
  .oversampling = 16U,
  .data_bits = 8U,
  .frame_length = 8U,
  .stop_bits = 2U,
  .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE
} ;

static XMC_DMA_CH_CONFIG_t U0C0_DMAChConfig =
{
  .dst_addr = (uint32_t)&(XMC_UART0_CH0->TBUF[0]),
  .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
  .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
  .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
  .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
  .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
  .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
  .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
  .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0,
  .enable_interrupt = true
};

static XMC_DMA_CH_CONFIG_t U0C1_DMAChConfig =
{
  .dst_addr = (uint32_t)&(XMC_UART0_CH1->TBUF[0]),
  .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
  .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
  .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
  .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
  .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
  .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
  .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
  .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_1,
  .enable_interrupt = true
};

static XMC_DMA_CH_CONFIG_t U1C0_DMAChConfig =
{
  .dst_addr = (uint32_t)&(XMC_UART1_CH0->TBUF[0]),
  .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
  .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
  .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
  .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
  .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
  .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
  .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
  .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR0_4,
  .enable_interrupt = true
};

static XMC_DMA_CH_CONFIG_t U1C1_DMAChConfig =
{
  .dst_addr = (uint32_t)&(XMC_UART1_CH1->TBUF[0]),
  .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
  .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
  .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
  .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
  .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
  .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
  .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
  .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
  .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR0_5,
  .enable_interrupt = true
};

void GPDMA0_0_IRQHandler(void)
{
  const uint8_t U0C0DMAChannel = 0;
  const uint8_t U0C1DMAChannel = 1;
  const uint8_t U1C0DMAChannel = 2;
  const uint8_t U1C1DMAChannel = 3;

  // Check DMA0.0 transfer complete
  if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U0C0DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
  {
    XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U0C0DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
    printf("U0C0 DMA Done!\n");
  }

  // Check DMA0.1 transfer complete
  if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U0C1DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
  {
    XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U0C1DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
    printf("U0C1 DMA Done!\n");
  }

  // Check DMA0.2 transfer complete
  if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U1C0DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
  {
    XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U1C0DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
    printf("U1C0 DMA Done!\n");
  }

  // Check DMA0.3 transfer complete
  if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U1C1DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
  {
    XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U1C1DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
    printf("U1C1 DMA Done!\n");
  }
}

void DMATEST(void)
{
  uint8_t n = 0;

  for (n = 0; n < BUFFER_LENGTH; n++)
  {
    DMXBufferU0C0[n] = n;
    DMXBufferU0C1[n] = n;
    DMXBufferU1C0[n] = n;
    DMXBufferU1C1[n] = n;
  }

  // Init General Purpose DMA 0
  XMC_DMA_Init(XMC_DMA0);

  //////////////////////////////////////////////////////////////////////
  initUARTDMA(DMXBufferU0C0, XMC_USIC0_CH0, 0, &U0C0_DMAChConfig, P1_5);
  initUARTDMA(DMXBufferU0C1, XMC_USIC0_CH1, 1, &U0C1_DMAChConfig, P2_5);
  initUARTDMA(DMXBufferU1C0, XMC_USIC1_CH0, 2, &U1C0_DMAChConfig, P0_5);
  initUARTDMA(DMXBufferU1C1, XMC_USIC1_CH1, 3, &U1C1_DMAChConfig, P0_1);
  //////////////////////////////////////////////////////////////////////
}

void initUARTDMA(uint8_t *Buffer, XMC_USIC_CH_t *USICChannel, uint8_t DMAChannel, XMC_DMA_CH_CONFIG_t *DMAChannelConfig, const XMC_GPIO_PORT_t *Port, const uint8_t Pin)
{
  // Init GPDMA0 using specified DMA config
  XMC_DMA_CH_Init(XMC_DMA0, DMAChannel, DMAChannelConfig);

  // Enable GPDMA channel event BLOCK_TRANSFER_COMPLETE
  XMC_DMA_CH_EnableEvent(XMC_DMA0, DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);

  // Route interrupt vector to the handler routine and enable DMA event handling
  BSP_IntVectSet(GPDMA0_0_IRQn, GPDMA0_0_IRQHandler);
  NVIC_SetPriority(GPDMA0_0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63, 0));
  NVIC_EnableIRQ(GPDMA0_0_IRQn);

  // Init UART Channel
  XMC_UART_CH_Init(USICChannel, &uart_config);

  // Enable UART Event
  XMC_UART_CH_EnableEvent(USICChannel, XMC_UART_CH_EVENT_TRANSMIT_BUFFER);
  XMC_USIC_CH_SetInterruptNodePointer(USICChannel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, 0);

  // Start UART Channel
  XMC_UART_CH_Start(USICChannel);

  // Make DMA ready
  XMC_USIC_CH_TriggerServiceRequest(USICChannel, 0);

  // Configure TX
  XMC_GPIO_SetMode(Port, Pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2);
  XMC_DMA_CH_SetBlockSize(XMC_DMA0, DMAChannel, BUFFER_LENGTH);
  XMC_DMA_CH_SetSourceAddress(XMC_DMA0, DMAChannel, (uint32_t)Buffer);

  // Enable DMA Channel
  XMC_DMA_CH_Enable(XMC_DMA0, DMAChannel);
}

[Felix (Gast)]

Die Lösung lag darin, dass in so einem Fall für die Channels 
unterschiedliche Service Request Numbers verwendet werden müssen:

Funktioniert falsch:
====================

U0C0 struct: .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0
U0C1 struct: .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_1
U1C0 struct; .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR0_4
U1C0 struct; .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR0_5

Funktioniert richtig:
=====================

U0C0 struct: .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0
U0C1 struct: .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2
U1C0 struct; .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR0_1
U1C0 struct; .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR1_3

Analog dazu müssen auch die XMC_USIC_CH_SetInterruptNodePointer() und 
XMC_USIC_CH_TriggerServiceRequest() entsprechend mit SR Number 0 oder 1 
aufgerufen werden.

[amelia (Gast)]

Hey,
I am working with a dog motor.
I wanted to send a 8bytes data via uart.
could you help me with it ?