1 | #define BUFFER_LENGTH 100
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2 |
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3 | volatile uint8_t DMXBufferU0C0[BUFFER_LENGTH];
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4 | volatile uint8_t DMXBufferU0C1[BUFFER_LENGTH];
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5 | volatile uint8_t DMXBufferU1C0[BUFFER_LENGTH];
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6 | volatile uint8_t DMXBufferU1C1[BUFFER_LENGTH];
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7 |
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8 | static XMC_UART_CH_CONFIG_t uart_config =
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9 | {
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10 | .baudrate = 250000U,
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11 | .oversampling = 16U,
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12 | .data_bits = 8U,
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13 | .frame_length = 8U,
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14 | .stop_bits = 2U,
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15 | .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE
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16 | } ;
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17 |
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18 | static XMC_DMA_CH_CONFIG_t U0C0_DMAChConfig =
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19 | {
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20 | .dst_addr = (uint32_t)&(XMC_UART0_CH0->TBUF[0]),
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21 | .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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22 | .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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23 | .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
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24 | .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
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25 | .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
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26 | .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
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27 | .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
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28 | .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
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29 | .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
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30 | .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0,
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31 | .enable_interrupt = true
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32 | };
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33 |
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34 | static XMC_DMA_CH_CONFIG_t U0C1_DMAChConfig =
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35 | {
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36 | .dst_addr = (uint32_t)&(XMC_UART0_CH1->TBUF[0]),
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37 | .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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38 | .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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39 | .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
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40 | .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
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41 | .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
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42 | .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
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43 | .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
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44 | .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
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45 | .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
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46 | .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC0_SR0_1,
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47 | .enable_interrupt = true
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48 | };
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49 |
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50 | static XMC_DMA_CH_CONFIG_t U1C0_DMAChConfig =
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51 | {
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52 | .dst_addr = (uint32_t)&(XMC_UART1_CH0->TBUF[0]),
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53 | .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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54 | .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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55 | .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
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56 | .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
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57 | .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
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58 | .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
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59 | .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
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60 | .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
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61 | .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
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62 | .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR0_4,
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63 | .enable_interrupt = true
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64 | };
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65 |
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66 | static XMC_DMA_CH_CONFIG_t U1C1_DMAChConfig =
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67 | {
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68 | .dst_addr = (uint32_t)&(XMC_UART1_CH1->TBUF[0]),
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69 | .src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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70 | .dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_8,
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71 | .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
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72 | .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE,
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73 | .src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
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74 | .dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
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75 | .transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA,
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76 | .transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
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77 | .dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE,
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78 | .dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_USIC1_SR0_5,
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79 | .enable_interrupt = true
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80 | };
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81 |
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82 | void GPDMA0_0_IRQHandler(void)
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83 | {
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84 | const uint8_t U0C0DMAChannel = 0;
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85 | const uint8_t U0C1DMAChannel = 1;
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86 | const uint8_t U1C0DMAChannel = 2;
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87 | const uint8_t U1C1DMAChannel = 3;
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88 |
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89 | // Check DMA0.0 transfer complete
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90 | if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U0C0DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
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91 | {
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92 | XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U0C0DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
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93 | printf("U0C0 DMA Done!\n");
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94 | }
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95 |
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96 | // Check DMA0.1 transfer complete
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97 | if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U0C1DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
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98 | {
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99 | XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U0C1DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
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100 | printf("U0C1 DMA Done!\n");
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101 | }
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102 |
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103 | // Check DMA0.2 transfer complete
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104 | if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U1C0DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
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105 | {
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106 | XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U1C0DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
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107 | printf("U1C0 DMA Done!\n");
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108 | }
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109 |
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110 | // Check DMA0.3 transfer complete
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111 | if (XMC_DMA_CH_GetEventStatus(XMC_DMA0, U1C1DMAChannel) == XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE)
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112 | {
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113 | XMC_DMA_CH_ClearEventStatus(XMC_DMA0, U1C1DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
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114 | printf("U1C1 DMA Done!\n");
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115 | }
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116 | }
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117 |
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118 | void DMATEST(void)
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119 | {
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120 | uint8_t n = 0;
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121 |
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122 | for (n = 0; n < BUFFER_LENGTH; n++)
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123 | {
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124 | DMXBufferU0C0[n] = n;
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125 | DMXBufferU0C1[n] = n;
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126 | DMXBufferU1C0[n] = n;
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127 | DMXBufferU1C1[n] = n;
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128 | }
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129 |
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130 | // Init General Purpose DMA 0
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131 | XMC_DMA_Init(XMC_DMA0);
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132 |
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133 | //////////////////////////////////////////////////////////////////////
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134 | initUARTDMA(DMXBufferU0C0, XMC_USIC0_CH0, 0, &U0C0_DMAChConfig, P1_5);
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135 | initUARTDMA(DMXBufferU0C1, XMC_USIC0_CH1, 1, &U0C1_DMAChConfig, P2_5);
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136 | initUARTDMA(DMXBufferU1C0, XMC_USIC1_CH0, 2, &U1C0_DMAChConfig, P0_5);
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137 | initUARTDMA(DMXBufferU1C1, XMC_USIC1_CH1, 3, &U1C1_DMAChConfig, P0_1);
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138 | //////////////////////////////////////////////////////////////////////
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139 | }
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140 |
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141 | void initUARTDMA(uint8_t *Buffer, XMC_USIC_CH_t *USICChannel, uint8_t DMAChannel, XMC_DMA_CH_CONFIG_t *DMAChannelConfig, const XMC_GPIO_PORT_t *Port, const uint8_t Pin)
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142 | {
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143 | // Init GPDMA0 using specified DMA config
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144 | XMC_DMA_CH_Init(XMC_DMA0, DMAChannel, DMAChannelConfig);
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145 |
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146 | // Enable GPDMA channel event BLOCK_TRANSFER_COMPLETE
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147 | XMC_DMA_CH_EnableEvent(XMC_DMA0, DMAChannel, XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
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148 |
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149 | // Route interrupt vector to the handler routine and enable DMA event handling
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150 | BSP_IntVectSet(GPDMA0_0_IRQn, GPDMA0_0_IRQHandler);
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151 | NVIC_SetPriority(GPDMA0_0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63, 0));
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152 | NVIC_EnableIRQ(GPDMA0_0_IRQn);
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153 |
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154 | // Init UART Channel
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155 | XMC_UART_CH_Init(USICChannel, &uart_config);
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156 |
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157 | // Enable UART Event
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158 | XMC_UART_CH_EnableEvent(USICChannel, XMC_UART_CH_EVENT_TRANSMIT_BUFFER);
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159 | XMC_USIC_CH_SetInterruptNodePointer(USICChannel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, 0);
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160 |
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161 | // Start UART Channel
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162 | XMC_UART_CH_Start(USICChannel);
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163 |
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164 | // Make DMA ready
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165 | XMC_USIC_CH_TriggerServiceRequest(USICChannel, 0);
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166 |
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167 | // Configure TX
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168 | XMC_GPIO_SetMode(Port, Pin, XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2);
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169 | XMC_DMA_CH_SetBlockSize(XMC_DMA0, DMAChannel, BUFFER_LENGTH);
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170 | XMC_DMA_CH_SetSourceAddress(XMC_DMA0, DMAChannel, (uint32_t)Buffer);
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171 |
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172 | // Enable DMA Channel
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173 | XMC_DMA_CH_Enable(XMC_DMA0, DMAChannel);
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174 | }
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