Forum: FPGA, VHDL & Co. Bitte um Hilfe bei Auswahl eines FPGA / Please help selecting an FPGA

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von Neugieriger (Gast)

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I'm just freshly diving into the world of FPGAs, but I have a certain 
use case in mind where I want to feed a PC's screen buffer content via 
an HDMI cable into a custom created board with (I hope) RasPi form 

I would appreciate your help in selecting an FPGA to support the 
following goals:

On that board I want to 'scan' the transferred buffer into multiple DACs 
in a FIFO manner with an independent DAC clock domain, so that I can 
achieve a constant DAC feeding bitstream while the HDMI receiver of 
course fills the buffer in bursts constrained by picture sync/HDMI 
protocol timing gaps.

As an HDMI receiver on that board I identified ADV7619 as a very serious 

I have a dream, but I'm of course also budget constrained.
So if you think I'm way too optimistic here with the following framework 
of numbers, please feel free to cut those numbers in half or even divide 
by 3 in order to get me grounded back into the realms of feasability:

With an FPGA+memory buffer based ADV7619-to-FIFO-to-DACs design I'm 
aiming at covering up to 5k*2k*24bits respectively 4k*2k*30bits virtual 
screen resolution at 60Hz.
If I'm judging right, then the ADV7619 (or a capable alternative) would 
(have to) deliver up to 10M*24*60 respectively 8M*30*60 = 14,4 Gbits/s = 
1,8 GBytes/s distributed over up to 48(+control) "FIFO input bus" pins 
in potentially "scanlinewise" bursts (at maybe up to 400 Mtransfers/s) 
into the hypothetical FPGA circuitry.

On the DAC side the same data shall be delivered via an independent 
clock by the FPGA circuitry on a 48(+control) pin wide "FIFO output bus" 
which directly and constantly feeds for example 6 8-bit DACs each at up 
to 300 Msamples/s.

About the actual FIFO buffer requirements:
I would roughly judge that the DAC side bus would never fall behind more 
than 10% of one frame, so its size would not necessaryly have to be 
larger than 24Mbits repectively 48 * (512 kbits/buspin).
those FIFO bit buffers be implemented directly within a reasonably 
priced FPGA ?
The max. average buffer transfer rate per FIFO bit (!) would have to be 
300 MHz in + 300 MHz out (on 2*48 different bit cells in parallel).
On the input side it would need an additional "burst speed line buffer" 
FIFO, which would have to buffer up to 2048 48-bit words at max. 400 MHz 
input clock (while being flushed to the main FIFO at 300 MHz).
would I rather have to add external RAM for the main FIFO ?
In that case that external (DDR3/4 ?) RAM would have to be able to 
transfer roughly 4 GBytes/s respectively 32 Gbits/s from/to the FPGA 
(which could be performed in alternating read and write bursts via 2 
additional FPGA implemented burst sized FIFOs). Could that throughput be 
achieved with only 1 RAM chip ?

If above numbers cannot be met at a reasonable budget; if the numbers 
would be "cut in half" - the following numbers would need to be met:
FPGA "input bus" burst speed max. 200 MHz (rather than 400)
FPGA "output bus" speed max. 150 MHz (rather than 300)
Main FIFO size 12 Mbits respectively (48 * (256 kbits/buspin))
If main FIFO must be external, then that RAM must support 2 GBytes/s in 

In both cases (300 MHz design or 150 MHz design) the required main FIFO 
size could be cut again in half under the assumption that with special 
HDMI sync timing the max. fallback of the DAC side would be limitable to 
just 5% of one frame.

What family/instance of FPGA would best fit above constraints on a 
budget ?


von alles fuer nen appl und ein ei (Gast)

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von Elbi (Gast)

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A digilent Atlys will do this. HDMI receiving is a bit tricky, hat there 
are ref designs that work.

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