STM32F103 und I2S Probleme

16774477, 0, 16777096, 0, 16777205, 0, 16777136, 0, 69, 0, 16777208, 0, 77, 0, 128, 0, 197, 0, 16777048, 0, 16776997, 0, 96, 0, 205, 0, 16777144, 0, 16777085, 0, 152, 0, 85, 0, 16777120, 0, 133, 0, 16777136, 0, 16777189, 0, 16777152, 0, 16777141, 0, 16777200, 0, 53, 0, 0, 0, 85, 0, 120, 0, 16777181, 0, 16777200, 0, 37, 0, 72, 0

#include "stm32f1xx.h"

#define BUFFER_LENGTH 64

#define FMT_SET() GPIOB->ODR |= GPIO_ODR_ODR2;

#define FMT_CLR() GPIOB->ODR &= ~(GPIO_ODR_ODR2);

#define MD0_SET() GPIOB->ODR |= GPIO_ODR_ODR10;

#define MD1_SET() GPIOB->ODR |= GPIO_ODR_ODR11;

#define MD0_CLR() GPIOB->ODR &= ~GPIO_ODR_ODR10;

#define MD1_CLR() GPIOB->ODR &= ~GPIO_ODR_ODR10;

void SysTick_Handler(void){

}

void GPIO_Init(){

  GPIOB->CRL |= GPIO_CRL_MODE0_0 | GPIO_CRL_MODE1_0 | GPIO_CRL_MODE2_0;

  GPIOB->CRH |= GPIO_CRH_MODE10_0 | GPIO_CRH_MODE11_0;

  GPIOB->CRL &= ~(GPIO_CRL_CNF0_0 | GPIO_CRL_CNF1_0 | GPIO_CRL_CNF2_0);

  GPIOB->CRH &= ~(GPIO_CRH_CNF10_0 | GPIO_CRH_CNF11_0);

}

void SysInit(void){

  FLASH->ACR = FLASH_ACR_PRFTBE;

  while(!(FLASH->ACR & FLASH_ACR_PRFTBS));

  FLASH->ACR |= FLASH_ACR_LATENCY_1;

  RCC->CR |= RCC_CR_HSEON;

  while(!(RCC->CR & RCC_CR_HSERDY));

  RCC->CFGR |= RCC_CFGR_PLLSRC;

  RCC->CFGR |= RCC_CFGR_PLLMULL9;

  RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

  RCC->CR |= RCC_CR_CSSON;

  RCC->CR |= RCC_CR_PLLON;

  while(!(RCC->CR & RCC_CR_PLLRDY));

  RCC->CFGR |= RCC_CFGR_SW_PLL;

  while(!(RCC->CFGR & RCC_CFGR_SWS_PLL));

  RCC->CFGR |= RCC_CFGR_MCOSEL_PLL_DIV2;

  RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN;

  GPIOA->CRH |= GPIO_CRH_CNF8_1;

  GPIOA->CRH &= ~GPIO_CRH_CNF8_0;

  GPIOA->CRH |= GPIO_CRH_MODE8_1 | GPIO_CRH_MODE8_0;

  SysTick_Config(7200000);

  GPIOC->CRL |= GPIO_CRL_MODE4_0 | GPIO_CRL_MODE5_0;

  GPIOC->CRL &= ~(GPIO_CRL_CNF4_0 | GPIO_CRL_CNF5_0);

  GPIOC->ODR |= GPIO_ODR_ODR4;

}

void I2S_Init(){

  RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;

/*  Procedure

  1. Select the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud

  rate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR

  register also has to be defined.**/

  SPI2->I2SPR = (SPI_I2SPR_MCKOE | 3);

  /*

  2. Select the CKPOL bit to define the steady level for the communication clock. Set the

  MCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to

  the external DAC/ADC audio component (the I2SDIV and ODD values should be

  computed depending on the state of the MCK output, for more details refer to

  Section 25.4.3).*/

  SPI2->I2SCFGR &= ~SPI_I2SCFGR_CKPOL;

  /*

  3. Set the I2SMOD bit in SPI_I2SCFGR to activate the I2S functionalities and choose the

  I2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the

  DATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit.

  Select also the I2S master mode and direction (Transmitter or Receiver) through the

  I2SCFG[1:0] bits in the SPI_I2SCFGR register.*/

  SPI2->I2SCFGR |= SPI_I2SCFGR_I2SMOD;

//  SPI2->I2SCFGR |= SPI_I2SCFGR_I2SSTD_0;

  SPI2->I2SCFGR |= SPI_I2SCFGR_DATLEN_0;

  SPI2->I2SCFGR |= SPI_I2SCFGR_I2SCFG;

  /*4. If needed, select all the potential interruption sources and the DMA capabilities by

  writing the SPI_CR2 register.

  */

  //<to do>

  /*

  5. The I2SE bit in SPI_I2SCFGR register must be set.

  WS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in

  SPI_I2SPR is set.*/

  /*

   * Pin B12 -> I2S2_WS; Alternate function, output, 50MHz

   * Pin B13 -> I2S2_CK; Alternate function, output, 50MHz

   * Pin B15 -> I2S2_SD; Input (Reset state)

   * Pin C6  -> I2S2_MCK; Alternate function, output, 50MHz

   */

  GPIOB->CRH &= ~(GPIO_CRH_CNF12 | GPIO_CRH_CNF13);

  GPIOB->CRH |= GPIO_CRH_MODE12 | GPIO_CRH_MODE13;

  GPIOB->CRH |= GPIO_CRH_CNF12_1 | GPIO_CRH_CNF13_1;

  GPIOC->CRL &= ~GPIO_CRL_CNF6;

  GPIOC->CRL |= GPIO_CRL_CNF6_1;

  GPIOC->CRL |= GPIO_CRL_MODE6_0 | GPIO_CRL_MODE6_1;

  MD0_CLR();

  MD1_CLR();

  FMT_CLR();

  SPI2->I2SCFGR |= SPI_I2SCFGR_I2SE;

return;

}

uint32_t I2S_ReadData(){

  //uint16_t data_received = 0;

  uint32_t data_complete = 0;

  while(!(SPI2->SR & SPI_SR_RXNE));

  data_complete = SPI2->DR;

  return data_complete;

}

int main(void)

{

  SysInit();

  GPIO_Init();

  I2S_Init();

  uint32_t data_received[BUFFER_LENGTH] = {0};

  uint16_t data_temp = 0;

  for(;;){

    for(uint8_t i = 0; i < BUFFER_LENGTH; i = i+2){

      data_temp = I2S_ReadData();

      data_received[i] = data_temp << 8;

      data_temp = I2S_ReadData();

      data_received[i] |= data_temp >> 8;

    }

    GPIOC->ODR ^= GPIO_ODR_ODR4;

  }

}