Quartus 2 clock domain LVDS input?.

Hello,

How can the clk domain most easily glitch-free in Quartus 2?
to be changed (Ip gene based)?
Background is an LVDS ADC which is connected to the FPGA and a
clk and a D returns. This can be easily received with the LVDS IP Block
become. Unfortunately, I can not do the same with this IP block from 
altera
activate the FIFO buffer which I can read out with the system clk.


thanks
iosman

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