ModelSim, Error: (vish-4008) Object 'clk' not found.

[Brunner Rita (Gast)]

ich versuche mit diese Code von Tutorial, kriegt aber folgend
Felermeldung:  Error: (vish-4008) Object 'clk' not found.

ich bedanke mich im voraus.

Code:(stim.do)
# Copyright 2006 Mentor Graphics Corporation
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
THE PROPERTY OF
# MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO
LICENSE TERMS.


# setup an oscillator on the CLK input
force clk 1 50  -r 100
force clk 0 100 -r 100

# reset the clock and then count to 100
force reset 1
run 100
if {[examine count] != 0} {
  echo "!!! Error: Reset failed. COUNT is [examine count]."
} else {
  echo "Reset OK. COUNT is [examine count]."
}

force reset 0
run 10000
if {[expr [examine -decimal count] != 100]} {
  echo "!!! Error: Counting to 100 failed. COUNT is [examine count]."
} else {
  echo "Test passed. COUNT is [examine count]."
}

counter.vhd:
--
-- Copyright 2006 Mentor Graphics Corporation
--
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO
LICENSE TERMS.
--

entity counter is
  port (count : buffer bit_vector(8 downto 1);
    clk   : in bit;
    reset : in bit);
end;

architecture only of counter is
  constant tpd_reset_to_count : time := 3 ns;
  constant tpd_clk_to_count   : time := 2 ns;

  function increment(val : bit_vector) return bit_vector
  is
    -- normalize the indexing
    alias input : bit_vector(val'length downto 1) is val;
    variable result : bit_vector(input'range) := input;
    variable carry : bit := '1';
  begin
    for i in input'low to input'high loop
      result(i) := input(i) xor carry;
      carry := input(i) and carry;
      exit when carry = '0';
    end loop;
    return result;
  end increment;
begin

  ctr:
  process(clk, reset)
  begin
    if (reset = '1') then
      if reset'event then
        count <= (others => '0') after tpd_reset_to_count;
      end if;
    elsif clk'event and (clk = '1') then
      count <= increment(count) after tpd_clk_to_count;
    end if;
  end process;

end only;

[Alexander Lindert (Gast)]

Dein Tutorial scheint mir nicht das beste zu sein! (Variablen anstatt
Signale, ....) Der Reseteingang, der alle Register auf den Anfangswert
bringt ist immer asynchron! (kein 'event)
Normalerweise schreibt man eine Testbench, mit stimuli processes.
In die do Datei werden vom transscript die Befehle der kompilierbaren
Datein kopiert, dann schreibt man
vsim testbench
do wave.do
run -all
Die wave.do erhält man wenn man nach dem einfügen der wave Signale auf
speichen geht.
Schreib eine testbench-ea.vhd:

entity testbench is
end entity;

architecture bhv of Testbench is
signal Clk : bit := '0';
signal nResetAsync : bit := '1'; -- n for negative logic
signal counter : buffer bit_vector(8 downto 1);
begin

Clk <= not Clk after 200 ns;

Stimuli: process is
begin
wait for 1 us;
nResetAsync <= '0';
wait for 256*2*200 ns;
report "Simulation finished, no failure!" serverity failure;
end process;

Counter: entity work.counter
  port map (count => counter,
    clk   => Clk,
    reset => nResetAsync);

end architecture;