STM32G0 SPI RXNE hängt sporadisch

uint8_t mySPITransmitReceiveBlocking(uint8_t *tx_data, uint8_t *rx_data, uint16_t size){

  uint8_t crcerror = 0;

  //  if CRC is enabled, reset CRC registers

  if(SPI2->CR1 & SPI_CR1_CRCEN){

    SPI2->CR1 &= ~SPI_CR1_CRCEN;

    SPI2->CR1 |= SPI_CR1_CRCEN;

  }

  __disable_irq();

  SPI2->CR1 |= SPI_CR1_SPE;  //  enable SPI

  for(int i = 1; i <= size; i++){

    while(!(SPI2->SR & SPI_SR_TXE));

    *((__IO uint8_t *)&SPI2->DR) = (uint8_t) *tx_data;

    tx_data++;

    if(i == size){  //  if CRC is enabled, send CRC next if transmission is finished

      if(SPI2->CR1 & SPI_CR1_CRCEN){

        SPI2->CR1 |= SPI_CR1_CRCNEXT;

      }

    }

    while(!(SPI2->SR & SPI_SR_RXNE));

    *rx_data = (*((__IO uint8_t *)&SPI2->DR));

    rx_data++;

  }

  //  CRC CHECK

  if(SPI2->CR1 & SPI_CR1_CRCEN){

    //  16 bit CRC is sent automatic, but must be read!

    while(!(SPI2->SR & SPI_SR_RXNE));

    uint8_t dummy = (*((__IO uint8_t *)&SPI2->DR));

    while(!(SPI2->SR & SPI_SR_RXNE));

    dummy = (*((__IO uint8_t *)&SPI2->DR));

    (void)dummy;  //  remove warning of ununsed variable

    //  check crc flag

    if(SPI2->SR & SPI_SR_CRCERR){

      //  wrong crc value

      SPI2->SR &= ~SPI_SR_CRCERR;

      crcerror = 1;

    }

  }

  __enable_irq();

  while(SPI2->SR & SPI_SR_BSY);

  SPI2->CR1 &= ~SPI_CR1_SPE;  //  disable SPI

  return crcerror;

}