Gast
#495150
ispLever : synplify schenkte mir das hier: * Warning: Forcing use of GSR for flip-flops and latches that do not specify sets or resets work.I2C(arch_i2c_1)-I2C_PROCESS.count_0_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.count_1_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.count_2_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.count_3_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_0_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_1_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_2_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_3_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_4_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_5_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_6_.Q work.I2C(arch_i2c_1)-I2C_PROCESS.shiftreg_7_.Q work.I2C(arch_i2c_1)-SCL_OLD.Q work.I2C(arch_i2c_1)-SDI_OLD.Q work.I2C(arch_i2c_1)-SDO.Q * ...was sagt mir das? danke schon mal... und an anderer stelle kommt sowas: * @W: CL112 :"C:\_STRAD~1\...c.vhd":36:1:36:2|Feedback mux created for signal SDO. Did you forget the set/reset assignment for this signal? @W: CL112 :"C:\_STRAD~1\...c.vhd":36:1:36:2|Feedback mux created for signal count[3:0]. Did you forget the set/reset assignment for this signal? @W: CL112 :"C:\_STRAD~1\...c.vhd":36:1:36:2|Feedback mux created for signal shiftreg[7:0]. Did you forget the set/reset assignment for this signal? @W: CL112 :"C:\_STRAD~1\...c.vhd":36:1:36:2|Feedback mux created for signal SDI_OLD. Did you forget the set/reset assignment for this signal? @W: CL112 :"C:\_STRAD~1\...c.vhd":36:1:36:2|Feedback mux created for signal SCL_OLD. Did you forget the set/reset assignment for this signal? * was habe ich hier evtl falsch gemacht?