Hallo Leute, ich habe ein Problem bei der Programmierung der LTC. Irgendwas scheine ich falsch gemacht zu haben, da der Timer LTC00 weder startet noch wenn ich einen Softwareinterrupt auslöse in die ISR springt. Bei einem Softwareinterrupt an die CPU gerichtet funktioniert die ISR aber. Wäre super wenn mir jemand sagen könnte was falsch ist. Der LTC00 soll ein Free-Running-Timer sein mit GPTA-Clock input. Der Interrupt soll bei overflow ausgelöst werden und die ISR abgearbeitet werden. Dann das Servicerequestflag zurückgesetzt werden und nach einer Verzögerungsschleife nochmals der Inerrupt ausgelöst werden. usw. (while(1)). Der Code wurde mit DAvE erzeugt und trotzdem haut es nicht hin! Hier der Code: ______________________________________________________________________ __ #include <MAIN.H> #include <stdafx.h> #include <stdio.h> #include <stdlib.h> #include <stdarg.h> #include <cint.h> #include <intrinsics.h> #include <WDTCON.h> volatile int quit=0; volatile int i=0; volatile int isrcount=0; volatile unsigned char c; void INT_viCPU2(void) { isrcount++; printf("isrcount cpu: %d\n", isrcount); } void GPTA_viSRN22(void) { isrcount++; printf("isrcount ltc: %d\n", isrcount); GPTA_SRS2_LTC00 = 0; } void GPTA_viSRN23(void) { isrcount++; printf("isrcount ltc: %d\n", isrcount); GPTA_SRS2_LTC02 = 0; } void SCU_vInit(void) { /// ----------------------------------------------------------------------- /// SCU Control: /// ----------------------------------------------------------------------- /// - the emulation trace on port 5 is disabled /// - pull-up/pull-down resistors are enabled during power down mode /// - the clock signal at pin CLKOUT is enabled SCU_CON = 0x00F10030; // load SCU control register /// ----------------------------------------------------------------------- /// Settings for the Power Management: /// ----------------------------------------------------------------------- /// - an internal hardware reset will be performed on exit from deep sleep MAIN_vResetENDINIT(); PMG_CON = 0x00000001; // load power management control register MAIN_vSetENDINIT(); /// ----------------------------------------------------------------------- /// Settings for the Watchdog Timer: /// ----------------------------------------------------------------------- /// - the watchdog timer is enabled /// - the input frequency is SYSCLK / 16384 /// - period in normal watchdog mode = 4,096 ms /// - period in time-out mode = 4,096 ms MAIN_vWriteWDTCON0(0xFFFC0000); WDT_CON1 = 0x00000000; // load watchdog control register 1 MAIN_vSetENDINIT(); /// ----------------------------------------------------------------------- /// Soft Reset Options: /// ----------------------------------------------------------------------- /// - use the last latched hardware configuration for booting after /// software reset (external inputs CFG[3:0]) /// - external devices are not reset on software reset through activating /// #HRST pin /// - the system timer is not reset on software reset } void INT_vInit(void) { /// ----------------------------------------------------------------------- /// Configuration of the used CPU Interrupts: /// ----------------------------------------------------------------------- /// - CPU2 service request node configuration: /// - CPU2 interrupt priority level (SRPN) = 9 /// - CPU2 CPU interrupt is selected CPU_SRC2 = 0x00001009; // set service request control register /// ----------------------------------------------------------------------- /// Configuration of Service Request Nodes 0 - 53: /// ----------------------------------------------------------------------- /// - SRN22 service request node configuration: /// - SRN22 interrupt priority level (SRPN) = 10 /// - SRN22 CPU interrupt is selected GPTA_SRC23 = 0x0000100B; // set service request control register _install_int_handler( 9, (void (*) (int)) INT_viCPU2, 0); _install_int_handler( 10, (void (*) (int)) GPTA_viSRN22, 0); _install_int_handler( 11, (void (*) (int)) GPTA_viSRN23, 0); } void GPTA_vInit(void) { /// ----------------------------------------------------------------------- /// Configuration of the Module Clock: /// ----------------------------------------------------------------------- /// - enable the GPTA module /// - clock divider for normal operation mode: System clock / 1 (= 16,0000 /// MHz; 62,500 ns ) /// - the GPTA module is stopped during sleep mode MAIN_vResetENDINIT(); GPTA_CLC = 0x00000100; // load clock control register MAIN_vSetENDINIT(); /// ----------------------------------------------------------------------- /// Configuration of Filter and Prescaler Cells 0 - 5: /// ----------------------------------------------------------------------- /// - FPC0 input selection: GPTA clock /// - FPC1 input selection: GPTA clock /// - FPC2 input selection: GPTA clock /// - FPC3 input selection: GPTA clock /// - FPC4 input selection: GPTA clock /// - FPC5 input selection: GPTA clock GPTA_FPCCTR1 = 0x00000000; // load FPC control register 1 GPTA_FPCCTR2 = 0x00222222; // load FPC control register 2 GPTA_FPCCOM0 = 0x00000000; // load FPC compare register 0 GPTA_FPCTIM0 = 0x00000000; // load FPC timer register 0 GPTA_FPCCOM1 = 0x00000000; // load FPC compare register 1 GPTA_FPCTIM1 = 0x00000000; // load FPC timer register 1 GPTA_FPCCOM2 = 0x00000000; // load FPC compare register 2 GPTA_FPCTIM2 = 0x00000000; // load FPC timer register 2 GPTA_FPCCOM3 = 0x00000000; // load FPC compare register 3 GPTA_FPCTIM3 = 0x00000000; // load FPC timer register 3 GPTA_FPCCOM4 = 0x00000000; // load FPC compare register 4 GPTA_FPCTIM4 = 0x00000000; // load FPC timer register 4 GPTA_FPCCOM5 = 0x00000000; // load FPC compare register 5 GPTA_FPCTIM5 = 0x00000000; // load FPC timer register 5 /// ----------------------------------------------------------------------- /// Configuration of Phase Discrimination Logic Cells 0 - 1: /// ----------------------------------------------------------------------- /// - PDL0 operates in '2 Sensor Mode' and provide DCM1 cell input with /// FPC2 output (= GPTA clock) /// - PDL0 provide DCM0 cell input with FPC0 output (= GPTA clock) /// - PDL1 operates in '2 Sensor Mode' and provide DCM3 cell input with /// FPC5 output (= GPTA clock) /// - PDL1 provide DCM2 cell input with FPC3 output (= GPTA clock) GPTA_PDLCTR = 0x00000000; // load PDL control register /// ----------------------------------------------------------------------- /// Configuration of Duty Cycle Measurement and Limit Checking Cells 0 - 3: /// ----------------------------------------------------------------------- /// - DCM0 input signal is GPTA clock /// - DCM0 capture the timer contents to CAV capture register on a falling /// input signal edge GPTA_DCMCTR0 = 0x00000000; // load DCM control register 0 GPTA_DCMCOV0 = 0x00000000; // load DCM capture/compare register 0 GPTA_DCMTIM0 = 0x00000000; // load DCM timer register 0 GPTA_DCMCAV0 = 0x00000000; // load DCM capture register 0 /// - DCM1 input signal is GPTA clock /// - DCM1 capture the timer contents to CAV capture register on a falling /// input signal edge GPTA_DCMCTR1 = 0x00000000; // load DCM control register 1 GPTA_DCMCOV1 = 0x00000000; // load DCM capture/compare register 1 GPTA_DCMTIM1 = 0x00000000; // load DCM timer register 1 GPTA_DCMCAV1 = 0x00000000; // load DCM capture register 1 /// - DCM2 input signal is GPTA clock /// - DCM2 capture the timer contents to CAV capture register on a falling /// input signal edge GPTA_DCMCTR2 = 0x00000000; // load DCM control register 2 GPTA_DCMCOV2 = 0x00000000; // load DCM capture/compare register 2 GPTA_DCMTIM2 = 0x00000000; // load DCM timer register 2 GPTA_DCMCAV2 = 0x00000000; // load DCM capture register 2 /// - DCM3 input signal is GPTA clock /// - DCM3 capture the timer contents to CAV capture register on a falling /// input signal edge GPTA_DCMCTR3 = 0x00000000; // load DCM control register 3 GPTA_DCMCOV3 = 0x00000000; // load DCM capture/compare register 3 GPTA_DCMTIM3 = 0x00000000; // load DCM timer register 3 GPTA_DCMCAV3 = 0x00000000; // load DCM capture register 3 /// ----------------------------------------------------------------------- /// Configuration of Digital Phase Locked Loop Cell: /// ----------------------------------------------------------------------- /// - use DCM0 output signal (= no output signal enabled) as PLL input /// - period of the PLL input signal in GPTA clocks = 0 /// - number of output pulses to be generated within one input signal /// period = 0 GPTA_PLLCTR = 0x00000000; // load PLL control register GPTA_PLLMTI = 0x00000000; // load PLL micro tick register GPTA_PLLSTP = 0x00000000; // load PLL step register GPTA_PLLREV = 0x00000000; // load PLL reload register GPTA_PLLCNT = 0x00000000; // load PLL counter register GPTA_PLLDTR = 0x00000000; // load PLL delta register /// ----------------------------------------------------------------------- /// Configuration of GPTA Clock Bus 0 - 7: /// ----------------------------------------------------------------------- /// - Clock bus signal 0: GPTA clock / 2^0 (= 16,000 MHz; 0,0625 µs) /// - Clock bus signal 1: PLL output /// - Clock bus signal 2: GPTA clock / 2^0 (= 16,000 MHz; 0,0625 µs) /// - Clock bus signal 3: DCM2 (= no output signal enabled) /// - Clock bus signal 4: GPTA clock / 2^0 (= 16,000 MHz; 0,0625 µs) /// - Clock bus signal 5: DCM0 (= no output signal enabled) /// - Clock bus signal 6: GPTA clock / 2^0 (= 16,000 MHz; 0,0625 µs) /// - Clock bus signal 7: GPTA clock / 2^0 (= 16,000 MHz; 0,0625 µs) GPTA_CKBCTR = 0x00000000; // load clock bus control register /// ----------------------------------------------------------------------- /// Configuration of Global Timers 0 - 1: /// ----------------------------------------------------------------------- /// - GT0 input is clock bus signal 0 (= GPTA clock / 2^0 (= 16,000 MHz; /// 0,0625 µs)) /// - GT0 compare flag is the 9th bit of the substraction result GPTA_GTCTR0 = 0x00000000; // load GT control register 0 GPTA_GTREV0 = 0x00000000; // load GT reload value register 0 GPTA_GTTIM0 = 0x00000000; // load GT timer register 0 /// - GT1 input is clock bus signal 0 (= GPTA clock / 2^0 (= 16,000 MHz; /// 0,0625 µs)) /// - GT1 compare flag is the 9th bit of the substraction result GPTA_GTCTR1 = 0x00000000; // load GT control register 1 GPTA_GTREV1 = 0x00000000; // load GT reload value register 1 GPTA_GTTIM1 = 0x00000000; // load GT timer register 1 /// ----------------------------------------------------------------------- /// Configuration of Global Timer Cells 0 - 31: /// ----------------------------------------------------------------------- /// ----------------------------------------------------------------------- /// Configuration of Local Timer Cells 0 - 63: /// ----------------------------------------------------------------------- /// Global Timer Cell 0 /// - LTC0 mode: free running timer /// - input is bus signal 7 (= GPTA clock / 2^0 (= 16,000 MHz; 0,0625 µs)) /// - action transfer: hold the LTC0 output by an local event only /// - force the selected output action after initialization /// - enable service request on the selected event (= free running timer) GPTA_LTCXR00 = 0x0000EFFE; // load LTC0 x register GPTA_LTCCTR00 = 0x0000450A; // load LTC0 control register /// Global Timer Cell 2 /// - LTC2 mode: free running timer /// - input is bus signal 7 (= GPTA clock / 2^0 (= 16,000 MHz; 0,0625 µs)) /// - action transfer: hold the LTC2 output by an local event only /// - force the selected output action after initialization /// - enable service request on the selected event (= free running timer) GPTA_LTCXR02 = 0x0000EFFE; // load LTC2 x register GPTA_LTCCTR02 = 0x0000450A; // load LTC2 control register /// ----------------------------------------------------------------------- /// Configuration of the used GPTA Port Pins: /// ----------------------------------------------------------------------- GPTA_OMR0 = 0x00000000; // load port line multiplex register 0 GPTA_OMR1 = 0x00000000; // load port line multiplex register 1 GPTA_OMR2 = 0x00000000; // load port line multiplex register 2 GPTA_OMR3 = 0x00000000; // load port line multiplex register 3 GPTA_EMGCTR0 = 0x00000000; // load emergency control register 0 GPTA_EMGCTR1 = 0x00000000; // load emergency control register 1 /// ----------------------------------------------------------------------- /// Configuration of Service Request Nodes 0 - 53: /// ----------------------------------------------------------------------- /// - SRN22 service request node configuration: /// - SRN22 interrupt priority level (SRPN) = 10 /// - SRN22 CPU interrupt is selected GPTA_SRC22 = 0x0000100A; // set service request control register /// ----------------------------------------------------------------------- /// Configuration of Trigger Events for the ADC: /// ----------------------------------------------------------------------- /// - ADC0 entry 0: GTC16 service request trigger (= cell is disabled) /// - ADC0 entry 1: LTC16 service request trigger (= cell is disabled) /// - ADC1 entry 0: GTC16 service request trigger (= cell is disabled) /// - ADC1 entry 1: LTC48 service request trigger (= cell is disabled) GPTA_ADCCTR = 0x00000000; // load ADC multiplex control register } void MAIN_vInit(void) { /// ----------------------------------------------------------------------- /// Clock System: /// ----------------------------------------------------------------------- /// - external clock frequency: 16,000 MHz /// - PLL operation (pin BYPASS = 0) /// - clock factor (N-factor): 10 (pins CLKSEL[2:0] = 0x2) /// - VCO output frequency: 160,000 MHz /// - clock divider (K-factor): 10 /// - system clock: 16,000 MHz MAIN_vResetENDINIT(); PLL_CLC = 0x00070000; // load PLL clock control register MAIN_vSetENDINIT(); /// ----------------------------------------------------------------------- /// Interrupt System: /// ----------------------------------------------------------------------- /// - four arbitration cycles (max. 255 interrupt sources) /// - two clocks per arbitration cycle MTCR(0xFE2C, 0x00000000); // load CPU interrupt control register ISYNC(); /// ----------------------------------------------------------------------- /// Peripheral Control Processor (PCP): /// ----------------------------------------------------------------------- /// - four arbitration cycles (max. 255 PCP channels) /// - two clocks per arbitration cycle /// - use Full Context save area (R[0] - R[7]) /// - channel start at context PC /// - the PCP error interrupt is disabled /// - PRAM partitioning is disabled /// - channel watchdog is disabled MAIN_vResetENDINIT(); PCP_CS = 0x00020800; // load PCP control and status register MAIN_vSetENDINIT(); MAIN_vResetENDINIT(); PCP_ICR = 0x00000000; // load PCP interrupt control register MAIN_vSetENDINIT(); // ----------------------------------------------------------------------- // Initialization of the Peripherals: // ----------------------------------------------------------------------- // initializes the System Control Unit (SCU) SCU_vInit(); // initializes the General Purpose Timer Array (GPTA) GPTA_vInit(); // initializes the Interrupt System (INT) INT_vInit(); /// ----------------------------------------------------------------------- /// System Start Conditions: /// ----------------------------------------------------------------------- /// - the CPU interrupt system is globally enabled ENABLE(); //// - the PCP interrupt system is globally disabled } int main(void) { MAIN_vInit(); while (1) { quit++; if(quit==3000){ printf("If Schleife\n"); CPU_SRC2_SETR = 1; GPTA_SRC22_SETR = 1; quit=0; } } return EXIT_SUCCESS; } ___________________________________________________________________ Wäre euch für die Hilfe wirklich dankbar! MFG Frank
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