Gast
#520819
Hallo!
Habe folgenden Testcode gebaut. Sinn soll später mal sein das ich ein
SRAM beschreiben kann.
Wie ihr aber sehen könnt denkt der Synthesizer das ich da weder mit
meiner Clock gearbeitet hab noch will er mein ram_a_data assignment
sehen.
Was hab ich denn da falsch gemacht?? Vielleicht kann ja jemand mal
schnell drüberschauhen...
Gruß,
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
port (
clock: in std_logic;
led : out std_logic_vector(7 downto 0);
ram_addr : out std_logic_vector(17 downto 0);
ram_we : out std_logic;
ram_oe : out std_logic;
ram_a_data : inout std_logic_vector(7 downto 0);
ram_a_ce : out std_logic;
ram_a_lb : out std_logic;
ram_a_ub : out std_logic );
end top;
architecture Behavioral of top is
signal srwrite : std_logic;
signal counter : std_logic_vector(10 downto 0) := (others => '0');
signal addr_in : std_logic_vector(17 downto 0) := (others => '0');
component sram is
port (
clock: in std_logic;
srwrite : in std_logic;
addr_in : in std_logic_vector(17 downto 0);
ram_addr : out std_logic_vector(17 downto 0);
ram_we : out std_logic;
ram_oe : out std_logic;
ram_a_data : inout std_logic_vector(7 downto 0);
ram_a_ce : out std_logic;
ram_a_lb : out std_logic;
ram_a_ub : out std_logic );
end component;
begin
swr: sram
port map (
clock => clock,
srwrite => srwrite,
addr_in => addr_in,
ram_addr => ram_addr,
ram_we => ram_we,
ram_oe => ram_oe,
ram_a_data => ram_a_data,
ram_a_ce => ram_a_ce,
ram_a_lb => ram_a_lb,
ram_a_ub => ram_a_ub );
process (clock)
begin
if (clock'event and clock = '1') then
if (counter < "00000001000") then
--write data
srwrite <= '1';
ram_a_data <= counter (7 downto 0);
addr_in <= addr_in + '1';
--ram_addr <= address;
-- conv_std_logic_vector(counter, 18); error multisource
-- srwrite <= '0';
-- ram_a_data <= ( others => 'Z' );
end if;
counter <= counter + 1;
end if;
end process;
end Behavioral;
Synthesizing Unit <sram>.
Related source file is "C:/VHDL/uart_send_sram/sram.vhd".
WARNING:Xst:647 - Input <clock> is never used.
WARNING:Xst:2563 - Inout <ram_a_data<0>> is never assigned. Tied to
value Z.
WARNING:Xst:2563 - Inout <ram_a_data<1>> is never assigned. Tied to
value Z.
WARNING:Xst:2563 - Inout <ram_a_data<2>> is never assigned. Tied to
value Z.
WARNING:Xst:2563 - Inout <ram_a_data<3>> is never assigned. Tied to
value Z.
WARNING:Xst:2563 - Inout <ram_a_data<4>> is never assigned. Tied to
value Z.
WARNING:Xst:2563 - Inout <ram_a_data<5>> is never assigned. Tied to
value Z.
WARNING:Xst:2563 - Inout <ram_a_data<6>> is never assigned. Tied to
value Z.
WARNING:Xst:2563 - Inout <ram_a_data<7>> is never assigned. Tied to
value Z.