Pins werden nicht angezeigt

Hallo
Habe gerade ein Design erstellt und jetzt wollte ich es auf den FPGA 
(Sparten 2) spielen und musste feststellen das er mit gewisse signal 
keinen Pins zuweisen lässt und ich finde den Fehler nicht! Habe das 
Projekt neu angelegt und er zeigt mir die Pins für "data_in" und 
"iobus_b" nicht an also ich kann den signalen keine Pins zuweisen! Bei 
allen anderen gehts ohne Probleme!

entity vga_toplevel is

  port (
    clk48        : in    std_logic;
    reset_n      : in    std_logic;
    data_in      : in    std_logic_vector(7 downto 0);
    address_out  : out   std_logic_vector(18 downto 0) := (others => 
'0');
    rgb_out      : out   std_logic_vector(3 downto 0)  := (others => 
'0');
    oe_out       : out   std_logic := '1';
    we_out       : out   std_logic := '1';
    hsync_out    : out   std_logic := '1';
    vsync_out    : out   std_logic := '1';
    busmux_o     : out   std_logic_vector(2 downto 0) := (others => 
'0');
    iobus_b      : inout std_logic_vector(7 downto 0) := (others => 
'0'));

end vga_toplevel;


architecture rtl of vga_toplevel is

  component vga_driver is
    port (
      clk48       : in    std_logic;
      reset_n     : in    std_logic;
      hpos_in     : in    std_logic_vector(9 downto 0);
      vpos_in     : in    std_logic_vector(9 downto 0);
      data_in     : in    std_logic_vector(7 downto 0);
      buttons_in  : in    std_logic_vector(7 downto 0);
      address_out : out   std_logic_vector(18 downto 0) := (others => 
'0');
      rgb_out     : out   std_logic_vector(3 downto 0)  := (others => 
'0');
      oe_out      : out   std_logic := '1';
      we_out      : out   std_logic := '1');

  end component vga_driver;


  component synctr is
    port (
      clk48       : in   std_logic;
      reset_n     : in   std_logic;
      hsync_out   : out  std_logic := '1';
      vsync_out   : out  std_logic := '1';
      vpos_out    : out  std_logic_vector(9 downto 0) := (others => 
'0');
      hpos_out    : out  std_logic_vector(9 downto 0) := (others => 
'0'));
  end component synctr;

  component ioctr is
    port (
      clk48    : in    std_logic;
      reset_n  : in    std_logic;
      buttons  : out   std_logic_vector(7 downto 0) := (others => '0');
      busmux_o : out   std_logic_vector(2 downto 0) := (others => '0');
      iobus_b  : inout std_logic_vector(7 downto 0));
  end component ioctr;

  --mem Signals
  signal mem_buttons  : std_logic_vector(7 downto 0) := (others => '0');
  signal mem_hpos     : std_logic_vector(9 downto 0) := (others => '0');
  signal mem_vpos     : std_logic_vector(9 downto 0) := (others => '0');

begin  -- rtl

  Ein_Ausgabe : ioctr
    port map (
      clk48      => clk48,
      reset_n    => reset_n,
      busmux_o   => busmux_o,
      iobus_b    => iobus_b,
      buttons    => mem_buttons);

  vga : vga_driver
    port map (
      clk48       => clk48,
      reset_n     => reset_n,
      hpos_in     => mem_hpos,
      vpos_in     => mem_vpos,
      buttons_in  => mem_buttons,
      data_in     => data_in,
      address_out => address_out,
      rgb_out     => rgb_out,
      oe_out      => oe_out,
      we_out      => we_out);

  Synch : synctr
    port map (
      clk48       => clk48,
      reset_n     => reset_n,
      hsync_out   => hsync_out,
      vsync_out   => vsync_out,
      vpos_out    => mem_vpos,
      hpos_out    => mem_hpos);

end rtl;

Wäre echt super wenn mir wer helfen könnte!?!?

Danke im vorhinein!

MFG Newbie