Undefined signals

library ieee;

use ieee.std_logic_1164.all;           

entity ErrGen_PNGEN7 is 

      port( 

      clock :  in std_logic;

            reset :  in std_logic;

            ErrEn :  in std_logic;  

           PNTrig : out std_logic; 

            PNOut : out std_logic; 

        ErrSeqOut : out std_logic    

    );

end entity ErrGen_PNGEN7;

architecture ErrGen_PNGEN7_arch of ErrGen_PNGEN7 is

        component PNGEN7 

            port( clock  :  in std_logic;

            reset  :  in std_logic;

            pntrig : out std_logic;

            pnser  : out std_logic );

   end component;

   component ErrGen 

      generic(Width : natural := 7);

       port( clock  :  in std_logic;

                   reset  :  in std_logic;

                  ErrEn  :  in std_logic;

             TxDIn  :  in std_logic;

               ErrSerOut  : out std_logic );

   end component;

    signal s_pnser   : std_logic; 

    begin 

    seq_gen: PNGEN7 port map( clock => clock,

                              reset => reset,

                             pntrig => PNTrig, 

                              pnser => s_pnser );

    ErrFade: ErrGen port map( clock => clock,

                              reset => reset,

                              ErrEn => ErrEn,  

                              TxDIn => s_pnser,

                          ErrSerOut => ErrSeqOut );         

             PNOut <= s_pnser;

end architecture;