Aldec Active HDL Student Edition

[Stephan (Gast)]

Schönen guten Abend!

Kennt / benutzt jemand die Student Edition von Aldec Active HDL?
http://www.aldec.com/education/students
Ich interessier mich dafür besonders wegen der graphischen 
Eingabemöglichkeiten (Bolckdiagramme, FSM-Editor). Welche 
Einschränkungen gibt es da gegenüber der Vollversion? Ist das trotzdem 
brauchbar?

Viele Grüße

Stephan

[Stefan H. (stefanhanke)]

Ich habs gerade mal installiert, zum Reinschnuppern ;-)
Die Release Notes verraten folgende:

Active-HDL 7.2 Student Edition Limitations
This Student Edition of Active-HDL 7.2 provides the following limitations in comparison to features available in a regular version:

Network installation is not available
Number of designs in a workspace is restricted to 1 design
Simulation performance: decreased x20, up to 500 instances
SystemVerilog and Accelerated Verilog simulation technology (SLP) is disabled
Off-line simulation (Post Simulation Debug) is disabled
Co-simulation of Handel-C blocks is disabled
Simulation of EDIF netlists is disabled
Batch mode (VSimSA) is not available
Testbench generation with results comparison in VHDL and Verilog is disabled
Testbench generation for VHDL and Verilog state machines is disabled
Block Diagram Editor can contain up to 30 symbols/fubs
State Diagram Editor can contain up to 30 states
Comparison of simulation results saved in AWF files is disabled in the GUI and the command line
Specification of custom stimuli saved in ASDB or VCD files is disabled
Import of all third-party projects is disabled
The Export to HTML/PDF option allows exporting block and state diagram that contain up to 30 symbols/fubs and 30 states, export of images to vector graphics is unavailable
Vendor simulation/schematic libraries are not installed
Additionally, the following options and tools are not available or limited
Accelerated Waveform Viewer
Advanced Dataflow Viewer
Advanced PDF Export
BDE Library Conversion
C Code Debug
Code Coverage, Expression Coverage, and Toggle Coverage
Code2Graphics Conversion Wizard
Conversion tools for the Standard and Accelerated Waveform Viewer
Design Flow Manager supports only the latest versions of the following tools:
HDL Synthesis
1. Mentor Graphics LeonardoSpectrum (incl. OEM editions)
2. Mentor Graphics Precision RTL Synthesis (incl. OEM editions)
3. Synplicity Synplify / Synplify Pro / Synplify Premier / Synplify Premier with Design Planner (incl. OEM editions)
3. Xilinx XST VHDL/Verilog (incl. available service packs)
Implementation
1. Actel Designer
2. Altera Quartus II
3. Lattice ispLEVER (incl. available service packs)
4. QuickLogic QuickWorks
5. Xilinx ISE/WebPack (incl. available service packs)

Refer to the Multivendor Flowchart topic in the Active-HDL on-line documentation or the Release Notes for the detailed information about versions of supported synthesis and implementation tools.

Design Profiler
Follow Object
HDE Actions Recorder/Player
LINT in VHDL and Verilog
Memory Viewer
Multi-process code generation for state machines
PLI/VHPI/VPI Wizard
Print Manager
Server Farm Integration
Third-party interfaces:
- Denali Memory Interface
- Debussy Interface
- Cover and DVM Interface
- Source Revision Control Interface
- SWIFT Interface
VHDL Signal Agent
Xtrace

[Stephan (Gast)]

Danke für deine spontane Experimentierfreudigkeit! Ich wollte es nicht 
gleich selber runterladen, weil mein Internetzugang zur Zeit nicht 
gerade breitbandig ist :-)
Aber das klingt ja garnichtmal so schlimm. Für kleine CPLDs sollte es 
wohl reichen.