1 | Active-HDL 7.2 Student Edition Limitations
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2 | This Student Edition of Active-HDL 7.2 provides the following limitations in comparison to features available in a regular version:
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3 |
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4 | Network installation is not available
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5 | Number of designs in a workspace is restricted to 1 design
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6 | Simulation performance: decreased x20, up to 500 instances
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7 | SystemVerilog and Accelerated Verilog simulation technology (SLP) is disabled
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8 | Off-line simulation (Post Simulation Debug) is disabled
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9 | Co-simulation of Handel-C blocks is disabled
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10 | Simulation of EDIF netlists is disabled
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11 | Batch mode (VSimSA) is not available
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12 | Testbench generation with results comparison in VHDL and Verilog is disabled
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13 | Testbench generation for VHDL and Verilog state machines is disabled
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14 | Block Diagram Editor can contain up to 30 symbols/fubs
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15 | State Diagram Editor can contain up to 30 states
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16 | Comparison of simulation results saved in AWF files is disabled in the GUI and the command line
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17 | Specification of custom stimuli saved in ASDB or VCD files is disabled
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18 | Import of all third-party projects is disabled
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19 | The Export to HTML/PDF option allows exporting block and state diagram that contain up to 30 symbols/fubs and 30 states, export of images to vector graphics is unavailable
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20 | Vendor simulation/schematic libraries are not installed
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21 | Additionally, the following options and tools are not available or limited
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22 | Accelerated Waveform Viewer
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23 | Advanced Dataflow Viewer
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24 | Advanced PDF Export
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25 | BDE Library Conversion
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26 | C Code Debug
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27 | Code Coverage, Expression Coverage, and Toggle Coverage
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28 | Code2Graphics Conversion Wizard
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29 | Conversion tools for the Standard and Accelerated Waveform Viewer
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30 | Design Flow Manager supports only the latest versions of the following tools:
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31 | HDL Synthesis
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32 | 1. Mentor Graphics LeonardoSpectrum (incl. OEM editions)
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33 | 2. Mentor Graphics Precision RTL Synthesis (incl. OEM editions)
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34 | 3. Synplicity Synplify / Synplify Pro / Synplify Premier / Synplify Premier with Design Planner (incl. OEM editions)
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35 | 3. Xilinx XST VHDL/Verilog (incl. available service packs)
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36 | Implementation
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37 | 1. Actel Designer
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38 | 2. Altera Quartus II
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39 | 3. Lattice ispLEVER (incl. available service packs)
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40 | 4. QuickLogic QuickWorks
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41 | 5. Xilinx ISE/WebPack (incl. available service packs)
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42 |
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43 | Refer to the Multivendor Flowchart topic in the Active-HDL on-line documentation or the Release Notes for the detailed information about versions of supported synthesis and implementation tools.
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44 |
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45 | Design Profiler
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46 | Follow Object
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47 | HDE Actions Recorder/Player
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48 | LINT in VHDL and Verilog
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49 | Memory Viewer
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50 | Multi-process code generation for state machines
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51 | PLI/VHPI/VPI Wizard
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52 | Print Manager
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53 | Server Farm Integration
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54 | Third-party interfaces:
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55 | - Denali Memory Interface
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56 | - Debussy Interface
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57 | - Cover and DVM Interface
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58 | - Source Revision Control Interface
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59 | - SWIFT Interface
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60 | VHDL Signal Agent
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61 | Xtrace
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