Forum: FPGA, VHDL & Co. erstes CPLD/FPGA Projekt ...


erstes CPLD/FPGA Projekt ...
von chriss (Gast)

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Hallo Zusammen!

Ich habe vor ca. 8Jahren einmal VHDL in einem Labor programmiert seitdem 
ist leider viel Zeit vergangen. Nun möchte ich einen CPLD/FPGA (Lattice 
MachXO ist ja was daszischen ;) ) also Levelshifter in einem 
Datenadressbus einsetzten.
Die Datenleitungen D[15..0] sind auf 1.8V Pegel die Datenleitungen 
D_LS[15..0] sind auf 3.3V Pegeln und gehen zu einem Ethernet Chip. (1.8V 
seite liegt die CPU).

naja nun hab ich versucht das ganze in VHDL zu schreiben, nur leider 
klappt es nicht so recht. Wenn der CPLD an die spannung angelegt wird 
treibt er den D - Bus auf 0 (alle 16pins!). geb ich die spannung weg 
sind die Pins High Z.

Vielleicht kann mir wer helfen bzw. einen Tipp geben? Danke

VHDL-Code: (signals TEST, TEST1 hab ich zum schluss hinzugefügt, vorher 
hab ich es direkt verbunden)
1
library ieee;

2
use ieee.std_logic_1164.all;

3
use ieee.numeric_std.all;

4
5
entity Eth_LevelShifter is

6
       port(

7
            D, D_LS: inout std_logic_vector(0 to 15);

8
            CS4, OE, RW, INT_LS, wai: in std_logic;

9
            CS4_LS, OE_LS, RW_LS, INT, wait_LS: out std_logic);

10
end Eth_LevelShifter;

11
12
architecture LevelShifter of Eth_LevelShifter is

13
14
signal TEST : std_logic_vector(0 to 15);

15
signal TEST1: std_logic_vector(0 to 15);

16
begin

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     databuf: process(CS4, RW)

18
     begin

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  TEST <= D;

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  TEST1 <= D_LS;

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     if CS4 = '0' then

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      if RW = '0' then

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       D <= "ZZZZZZZZZZZZZZZZ";

24
       D_LS <= TEST;

25
      else

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       D_LS <= "ZZZZZZZZZZZZZZZZ";

27
       D <= TEST1;

28
      end if;

29
     else

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      D <= "ZZZZZZZZZZZZZZZZ";

31
      D_LS <= "ZZZZZZZZZZZZZZZZ";

32
     end if;

33
     end process databuf;

34
35
     csbuf: process (CS4)

36
      begin

37
       if CS4='0' then

38
        CS4_LS <= '0';

39
       else

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        CS4_LS <= '1';

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       end if;

42
     end process csbuf;

43
44
     process (OE)

45
     begin

46
      if OE='0' then

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       OE_LS <= '0';

48
      else

49
       OE_LS <= '1';

50
      end if;

51
     end process;

52
53
     process (RW)

54
     begin

55
      if RW='0' then

56
       RW_LS <= '0';

57
      else

58
       RW_LS <= '1';

59
      end if;

60
     end process;

61
62
     process (INT_LS)

63
     begin

64
      if INT_LS='0' then

65
       INT <= '0';

66
      else

67
       INT <= '1';

68
      end if;

69
     end process;

70
    

71
     wait_buf: process (wai)

72
  begin

73
    if wai='0' then

74
      wait_LS <= '0';

75
    else

76
      wait_LS <= '1';

77
    end if;

78
  end process wait_buf;

79
end LevelShifter;


statt "KEEPER" hab ich auch schon "NONE" probiert
1
OMMERCIAL ;

2
BLOCK RESETPATHS ;

3
BLOCK ASYNCPATHS ;

4
LOCATE COMP "D(0)" SITE "20" ;

5
LOCATE COMP "D(1)" SITE "21" ;

6
LOCATE COMP "D(10)" SITE "37" ;

7
LOCATE COMP "D(11)" SITE "38" ;

8
LOCATE COMP "D(12)" SITE "39" ;

9
LOCATE COMP "D(13)" SITE "43" ;

10
LOCATE COMP "D(14)" SITE "44" ;

11
LOCATE COMP "D(15)" SITE "45" ;

12
LOCATE COMP "D(2)" SITE "22" ;

13
LOCATE COMP "D(3)" SITE "23" ;

14
LOCATE COMP "D(4)" SITE "27" ;

15
LOCATE COMP "D(5)" SITE "29" ;

16
LOCATE COMP "D(6)" SITE "30" ;

17
LOCATE COMP "D(7)" SITE "32" ;

18
LOCATE COMP "D(8)" SITE "34" ;

19
LOCATE COMP "D(9)" SITE "36" ;

20
LOCATE COMP "D_LS(0)" SITE "81" ;

21
LOCATE COMP "D_LS(1)" SITE "80" ;

22
LOCATE COMP "D_LS(10)" SITE "69" ;

23
LOCATE COMP "D_LS(11)" SITE "68" ;

24
LOCATE COMP "D_LS(12)" SITE "67" ;

25
LOCATE COMP "D_LS(13)" SITE "66" ;

26
LOCATE COMP "D_LS(14)" SITE "65" ;

27
LOCATE COMP "D_LS(15)" SITE "64" ;

28
LOCATE COMP "D_LS(2)" SITE "79" ;

29
LOCATE COMP "D_LS(3)" SITE "78" ;

30
LOCATE COMP "D_LS(4)" SITE "77" ;

31
LOCATE COMP "D_LS(5)" SITE "76" ;

32
LOCATE COMP "D_LS(6)" SITE "73" ;

33
LOCATE COMP "D_LS(7)" SITE "72" ;

34
LOCATE COMP "D_LS(8)" SITE "71" ;

35
LOCATE COMP "D_LS(9)" SITE "70" ;

36
LOCATE COMP "CS4" SITE "8" ;

37
LOCATE COMP "RW" SITE "5" ;

38
LOCATE COMP "CS4_LS" SITE "96" ;

39
LOCATE COMP "INT" SITE "50" ;

40
LOCATE COMP "OE_LS" SITE "100" ;

41
LOCATE COMP "RW_LS" SITE "99" ;

42
IOBUF PORT "CS4_LS" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

43
IOBUF PORT "OE_LS" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

44
IOBUF PORT "RW_LS" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

45
IOBUF PORT "D_LS(0)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

46
IOBUF PORT "D_LS(1)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

47
IOBUF PORT "D_LS(10)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

48
IOBUF PORT "D_LS(11)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

49
IOBUF PORT "D_LS(12)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

50
IOBUF PORT "D_LS(13)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

51
IOBUF PORT "D_LS(14)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

52
IOBUF PORT "D_LS(15)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

53
IOBUF PORT "D_LS(2)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

54
IOBUF PORT "D_LS(3)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

55
IOBUF PORT "D_LS(4)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

56
IOBUF PORT "D_LS(5)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

57
IOBUF PORT "D_LS(6)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

58
IOBUF PORT "D_LS(7)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

59
IOBUF PORT "D_LS(8)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

60
IOBUF PORT "D_LS(9)" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

61
IOBUF PORT "CS4" IO_TYPE=LVCMOS18 DRIVE=NA PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

62
IOBUF PORT "RW" IO_TYPE=LVCMOS18 DRIVE=NA PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

63
IOBUF PORT "INT" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

64
IOBUF PORT "D(0)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

65
IOBUF PORT "D(1)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

66
IOBUF PORT "D(10)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

67
IOBUF PORT "D(11)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

68
IOBUF PORT "D(12)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

69
IOBUF PORT "D(13)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

70
IOBUF PORT "D(14)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

71
IOBUF PORT "D(15)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

72
IOBUF PORT "D(2)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

73
IOBUF PORT "D(3)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

74
IOBUF PORT "D(4)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

75
IOBUF PORT "D(5)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

76
IOBUF PORT "D(6)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

77
IOBUF PORT "D(7)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

78
IOBUF PORT "D(8)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

79
IOBUF PORT "D(9)" IO_TYPE=LVCMOS18 DRIVE=8 PULLMODE=KEEPER SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

80
LOCATE COMP "CS4_LS" SITE "96" ;

81
LOCATE COMP "D(0)" SITE "20" ;

82
LOCATE COMP "CS4" SITE "8" ;

83
LOCATE COMP "INT" SITE "50" ;

84
LOCATE COMP "RW_LS" SITE "99" ;

85
LOCATE COMP "OE_LS" SITE "100" ;

86
LOCATE COMP "D_LS(15)" SITE "64" ;

87
LOCATE COMP "D_LS(14)" SITE "65" ;

88
LOCATE COMP "D_LS(13)" SITE "66" ;

89
LOCATE COMP "D_LS(12)" SITE "67" ;

90
LOCATE COMP "D_LS(11)" SITE "68" ;

91
LOCATE COMP "D_LS(10)" SITE "69" ;

92
LOCATE COMP "D_LS(9)" SITE "70" ;

93
LOCATE COMP "D_LS(8)" SITE "71" ;

94
LOCATE COMP "D_LS(7)" SITE "72" ;

95
LOCATE COMP "D_LS(6)" SITE "73" ;

96
LOCATE COMP "D_LS(5)" SITE "76" ;

97
LOCATE COMP "D_LS(4)" SITE "77" ;

98
LOCATE COMP "D_LS(3)" SITE "78" ;

99
LOCATE COMP "D_LS(2)" SITE "79" ;

100
LOCATE COMP "D_LS(1)" SITE "80" ;

101
LOCATE COMP "D_LS(0)" SITE "81" ;

102
LOCATE COMP "D(15)" SITE "45" ;

103
LOCATE COMP "D(14)" SITE "44" ;

104
LOCATE COMP "D(13)" SITE "43" ;

105
LOCATE COMP "D(12)" SITE "39" ;

106
LOCATE COMP "D(11)" SITE "38" ;

107
LOCATE COMP "D(10)" SITE "37" ;

108
LOCATE COMP "D(9)" SITE "36" ;

109
LOCATE COMP "D(8)" SITE "34" ;

110
LOCATE COMP "D(7)" SITE "32" ;

111
LOCATE COMP "D(6)" SITE "30" ;

112
LOCATE COMP "D(5)" SITE "29" ;

113
LOCATE COMP "D(4)" SITE "27" ;

114
LOCATE COMP "D(3)" SITE "23" ;

115
LOCATE COMP "D(2)" SITE "22" ;

116
LOCATE COMP "D(1)" SITE "21" ;

117
LOCATE COMP "RW" SITE "5" ;

118
LOCATE COMP "INT_LS" SITE "63" ;

119
LOCATE COMP "OE" SITE "4" ;

120
LOCATE COMP "CS4_LS" SITE "96" ;

121
LOCATE COMP "D(0)" SITE "20" ;

122
LOCATE COMP "CS4" SITE "8" ;

123
LOCATE COMP "INT" SITE "50" ;

124
LOCATE COMP "RW_LS" SITE "99" ;

125
LOCATE COMP "OE_LS" SITE "100" ;

126
LOCATE COMP "D_LS(15)" SITE "64" ;

127
LOCATE COMP "D_LS(14)" SITE "65" ;

128
LOCATE COMP "D_LS(13)" SITE "66" ;

129
LOCATE COMP "D_LS(12)" SITE "67" ;

130
LOCATE COMP "D_LS(11)" SITE "68" ;

131
LOCATE COMP "D_LS(10)" SITE "69" ;

132
LOCATE COMP "D_LS(9)" SITE "70" ;

133
LOCATE COMP "D_LS(8)" SITE "71" ;

134
LOCATE COMP "D_LS(7)" SITE "72" ;

135
LOCATE COMP "D_LS(6)" SITE "73" ;

136
LOCATE COMP "D_LS(5)" SITE "76" ;

137
LOCATE COMP "D_LS(4)" SITE "77" ;

138
LOCATE COMP "D_LS(3)" SITE "78" ;

139
LOCATE COMP "D_LS(2)" SITE "79" ;

140
LOCATE COMP "D_LS(1)" SITE "80" ;

141
LOCATE COMP "D_LS(0)" SITE "81" ;

142
LOCATE COMP "D(15)" SITE "45" ;

143
LOCATE COMP "D(14)" SITE "44" ;

144
LOCATE COMP "D(13)" SITE "43" ;

145
LOCATE COMP "D(12)" SITE "39" ;

146
LOCATE COMP "D(11)" SITE "38" ;

147
LOCATE COMP "D(10)" SITE "37" ;

148
LOCATE COMP "D(9)" SITE "36" ;

149
LOCATE COMP "D(8)" SITE "34" ;

150
LOCATE COMP "D(7)" SITE "32" ;

151
LOCATE COMP "D(6)" SITE "30" ;

152
LOCATE COMP "D(5)" SITE "29" ;

153
LOCATE COMP "D(4)" SITE "27" ;

154
LOCATE COMP "D(3)" SITE "23" ;

155
LOCATE COMP "D(2)" SITE "22" ;

156
LOCATE COMP "D(1)" SITE "21" ;

157
IOBUF PORT "INT_LS" IO_TYPE=LVCMOS33 DRIVE=NA PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

158
LOCATE COMP "INT_LS" SITE "63" ;

159
LOCATE COMP "RW" SITE "5" ;

160
IOBUF PORT "OE" IO_TYPE=LVCMOS18 DRIVE=NA PULLMODE=NONE SLEWRATE=FAST OPENDRAIN=OFF INF=OFF ;

161
LOCATE COMP "OE" SITE "4" ;

162
LOCATE COMP "wait_LS" SITE "97" ;

163
LOCATE COMP "wai" SITE "7" ;

164
IOBUF PORT "wait_LS" IO_TYPE=LVCMOS33 PULLMODE=NONE ;

165
IOBUF PORT "wai" IO_TYPE=LVCMOS18 PULLMODE=NONE ;


  


  




  

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    Re: erstes CPLD/FPGA Projekt ...
  


  

    

      von
      
        Johnsn (Gast)
      
      


      
    


    

      
    

    

    

  
  


  

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Irgendwelche Warnings in der Synthese?

  


  




  

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    Re: erstes CPLD/FPGA Projekt ...
  


  

    

      von
      
        chriss (Gast)
      
      


      
    


    

      
    

    

    

  
  


  

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nein leider nichts ...
ich hab es auch schon mal mit symbols im schematic probiert, da gab es 
massig probleme, dann bin ich aber auf vhdl umgestiegen und er hat keine 
warnings bzg. errors ausgegeben.

sonst einen tipp?

  


  




  

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    Re: erstes CPLD/FPGA Projekt ...
  


  

    

      von
      
        Klaus F.
        (kfalser)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Versuche es mal so :

D    <= D_LS when CS = '0' and RW = '1' else (others => 'Z');
D_LS <= D    when CS = '0' and RW = '0' else (others => 'Z');

RW_LS <= RW;
...

Das ganze außerhalb eines Prozesses.

Klaus

  


  




  

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    Re: erstes CPLD/FPGA Projekt ...
  


  

    

      von
      
        Klaus F.
        (kfalser)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Außerdem solltest Du Keeper deaktivieren!

  


  




  

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    Re: erstes CPLD/FPGA Projekt ...
  


  

    

      von
      
        chriss (Gast)
      
      


      
    


    

      
    

    

    

  
  


  

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Danke, für deinen Tipp, aber leider hab ich noch immer lauter lows auf 
den leitungen wenn der CPL aktiviert wird/ist.

hat noch wer eine idee?

danke
Gr
chriss

  


  




  

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