Filter Bauen mit VHDL

Hallo
ich bin VHDl Anfänger  und moechte ein Filter bzw. CIC filter bauen . 
Ich habe vorher  eine Mischung von der sinus/cosinus mit des ADC-Daten 
gemacht und möchte die Ergebnissen Filter.
Ungefähr          W= cos*ADC_DATEN;
                  Z= Sin*ADC_DATEN;
Eine CIC-Filter gibt es schon in Xilinx IP-Core aber wie Kann ich das 
machen? Hat jemand einen Tipp fuer mich?


Danke

Gruß.
Auguste


-- You must compile the wrapper file CICDecimator.vhd when simulating
-- the core, CICDecimator. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY CICDecimator IS
  port (
  DIN: IN std_logic_VECTOR(9 downto 0);
  ND: IN std_logic;
  RFD: OUT std_logic;
  CLK: IN std_logic;
  DOUT: OUT std_logic_VECTOR(22 downto 0);
  RDY: OUT std_logic;
  LD_DIN: IN std_logic_VECTOR(13 downto 0);
  WE: IN std_logic);
END CICDecimator;

ARCHITECTURE CICDecimator_a OF CICDecimator IS
-- synthesis translate_off
component wrapped_CICDecimator
  port (
  DIN: IN std_logic_VECTOR(9 downto 0);
  ND: IN std_logic;
  RFD: OUT std_logic;
  CLK: IN std_logic;
  DOUT: OUT std_logic_VECTOR(22 downto 0);
  RDY: OUT std_logic;
  LD_DIN: IN std_logic_VECTOR(13 downto 0);
  WE: IN std_logic);
end component;

-- Configuration specification
  for all : wrapped_CICDecimator use entity 
XilinxCoreLib.C_CIC_V3_0(behavioral)
    generic map(
      c_differential_delay => 1,
      c_sample_rate_change_max => 16383,
      c_number_channels => 1,
      c_filter_type => 2,
      c_result_width => 23,
      c_enable_rlocs => 0,
      c_sample_rate_change => 4,
      c_latency => 1,
      c_sample_rate_change_min => 4,
      c_sample_rate_change_type => 1,
      c_data_width => 10,
      c_stages => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_CICDecimator
    port map (
      DIN => DIN,
      ND => ND,
      RFD => RFD,
      CLK => CLK,
      DOUT => DOUT,
      RDY => RDY,
      LD_DIN => LD_DIN,
      WE => WE);
-- synthesis translate_on

END CICDecimator_a;