Gast
#636773
Hallo
Ich habe folgenden Code:
library ieee;
use ieee.std_logic_1164.all;
entity fteiler is
Port ( CLOCK : in std_logic;
CLK1 : out std_logic;
CLK2 : out std_logic);
end fteiler;
architecture behavior of fteiler is
signal count_int : std_logic_vector(0 to 19) := "00000000000000000000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event
then
count_int <= count_int + '1';
end if;
end process;
CLK1 <= count_int(19);
CLK2 <= count_int(18);
end behavior;
------------------------------------------------------------------
und bekomme dazu folgende Fehlermeldund:
Error (10327): VHDL error at fteiler.vhd(19): can't determine definition
of operator ""+"" -- found 0 possible definitions
Kann mir jemand weiter helfen?