Man optimiert nicht code, man optimiert hardware. Heisst du legst fest
was du brauchst (Zähler,Register,Multiplexer,...) beschreibst die so in
VHDL das das das Synthesetool die als Zähler,Register,Multiplexer,...
erkennst. Checkst dann noch im synthesereport (*.syr) das dem so ist und
fertig der Zähler.
Vergiss C mit sizeof(int) >sizeof(char) und so, entscheident ist wie die
synthese deine signal in Hardware umsetzt. Alles weiter wie beim
Vorredner.
Der code:
---------
1 | USE ieee.std_logic_1164.ALL;
|
2 |
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3 | ENTITY counter IS
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4 | PORT (
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5 | clk_i : IN std_logic;
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6 | tick_o : OUT std_logic);
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7 | END counter;
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8 |
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9 | ARCHITECTURE behave OF counter IS
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10 |
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11 | SUBTYPE T_COUNT_640 IS integer RANGE 639 DOWNTO 0;
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12 | SIGNAL count_q : t_count_640 := T_COUNT_640'high;
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13 | --
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14 | SIGNAL overflow : std_logic;
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15 |
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16 | BEGIN -- behave
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17 |
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18 | PROCESS(clk_i)
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19 | BEGIN
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20 | IF rising_edge(clk_i) THEN
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21 | IF overflow = '1' THEN
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22 | count_q <= t_count_640'high;
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23 | ELSE
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24 | count_q <= count_q - 1;
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25 | END IF;
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26 | END IF;
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27 | END PROCESS;
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28 | overflow <= '1' WHEN count_q = T_COUNT_640'low ELSE '0';
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29 |
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30 | tick_o <= overflow;
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31 | END behave;
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der Synthesereport:
-------------------
Synthesizing Unit <counter>.
Related source file is "/home/urban/elektro/cpld_count/count.vhd".
Found 10-bit down counter for signal <count_q>.
Summary:
inferred 1 Counter(s).
Unit <counter> synthesized.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this
technology.
========================================================================
=
HDL Synthesis Report
Macro Statistics
# Counters : 1
10-bit down counter : 1
========================================================================
=
========================================================================
=
* Advanced HDL Synthesis
*
========================================================================
=
========================================================================
=
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 1
10-bit down counter : 1
========================================================================
=
========================================================================
=
* Low Level Synthesis
*
========================================================================
=
Optimizing unit <counter> ...
implementation constraint: INIT=s : count_q_9
implementation constraint: INIT=r : count_q_8
implementation constraint: INIT=r : count_q_7
implementation constraint: INIT=s : count_q_6
implementation constraint: INIT=s : count_q_5
implementation constraint: INIT=s : count_q_4
implementation constraint: INIT=s : count_q_3
implementation constraint: INIT=s : count_q_2
implementation constraint: INIT=s : count_q_1
implementation constraint: INIT=s : count_q_0
========================================================================
=
* Partition Report
*
========================================================================
=
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
========================================================================
=
* Final Report
*
========================================================================
=
Final Results
Top Level Output File Name : counter
Output Format : NGC
Optimization Goal : Area
Keep Hierarchy : YES
Target Technology : XC9500 CPLDs
Macro Preserve : YES
XOR Preserve : YES
wysiwyg : NO
Design Statistics
# IOs : 2
Cell Usage :
# BELS : 54
# AND2 : 5
# AND3 : 3
# INV : 22
# OR2 : 15
# XOR2 : 9
# FlipFlops/Latches : 10
# FD : 10
# IO Buffers : 2
# IBUF : 1
# OBUF : 1
========================================================================
=
Der Schlussreport
------------------
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
11 /36 ( 31%) 13 /180 ( 7%) 10 /72 ( 14%) 10 /36 ( 28%) 2 /34
( 6%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 0/18 0/36 0 0/90 0/17
FB2 11/18 10/36 10 13/90 1/17
----- ----- ----- -----
11/36 10/72 13/180 1/34
