If und Port-Map Problem

keine Instanziierung im Prozeß, port map ist nur direct in der 
architecture erlaubt, grad ein generate oder block drumherum geht.

Welche Hardware willst du den bauen?

Ich spiele damit nur herum.
Ich habe auf meinem EVA-Board vier taster, vier schalter und vier 7-Seg. 
anzeigen.

an den BCD- Schaltern wird ein Wert eingestellt und je nach schalter 
wird dieser werte einer der 7-Seg. anzeigen weitergeleitet.

library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity bcd is
port(   s:    in std_logic_vector(3 downto 0);
    k:    in std_logic_vector(3 downto 0);
    lx1:  out std_logic_vector(6 downto 0);
    lx2:  out std_logic_vector(6 downto 0);
    lx3:  out std_logic_vector(6 downto 0);
    lx4:  out std_logic_vector(6 downto 0);
    clk_50:  in  std_logic
  );
end bcd;
-- 
------------------------------------------------------------------------ 
-
architecture struct of bcd is


  component led_coder is
  port   (
      schalter:  in std_logic_vector(3 downto 0);
      led:    out std_logic_vector(6 downto 0)
      );
  end component;

begin

    auswahl:process(clk_50)
    begin

    L1:
    if (k = "0001") GENERATE
        P1:led_coder port map ((schalter=>s, led=>lx1));
    end GENERATE;

    L2:
    if (k = "0010") GENERATE
        P2:led_coder port map ((schalter=>s, led=>lx2));
    end GENERATE;

    L3:
    if (k = "0100") GENERATE
        P3:led_coder port map ((schalter=>s, led=>lx3));
    end GENERATE;

    L4:
    if (k = "1000") GENERATE
        P4:led_coder port map ((schalter=>s, led=>lx4));
    end GENERATE;


    end process;
end struct;


geht leider auch nicht :(

Auf die folgende Art habe ich das problem gelöst :


library ieee;
use ieee.std_logic_1164.all;

entity led_coder is
  port( schalter : in std_logic_vector(3 downto 0);
      led :  out std_logic_vector(6 downto 0);
      aktiv: in std_logic
     );

end led_coder;


architecture behv of led_coder is
begin

  process  (schalter)
  begin
    if(aktiv='0') then
    case schalter is
                  -- GFEDCBA
      when "0000" => led <= NOT "0111111";
      when "0001" => led <= NOT "0000110";
      when "0010" => led <= NOT "1011011";
      when "0011" => led <= NOT "1001111";
      when "0100" => led <= NOT "1100110";
      when "0101" => led <= NOT "1101101";
      when "0110" => led <= NOT "1111101";
      when "0111" => led <= NOT "0000111";
      when "1000" => led <= NOT "1111111";
      when "1001" => led <= NOT "1101111";
      when others => led <= "ZZZZZZZ";
    end case;
    end if;
  end process;
end behv;

-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity bcd is
port(   s:    in std_logic_vector(3 downto 0);
    k1:    in std_logic;
    k2:    in std_logic;
    k3:    in std_logic;
    k4:    in std_logic;
    lx1:  out std_logic_vector(6 downto 0);
    lx2:  out std_logic_vector(6 downto 0);
    lx3:  out std_logic_vector(6 downto 0);
    lx4:  out std_logic_vector(6 downto 0)

  );
end bcd;
-- 
------------------------------------------------------------------------ 
-
architecture struct of bcd is

  component led_coder is
  port(schalter:   in std_logic_vector(3 downto 0);
     led:     out std_logic_vector(6 downto 0);
     aktiv:     in std_logic
     );
  end component;

begin

    P1: led_coder port map (schalter=>s, led=>lx1, aktiv=>k1);
    P2: led_coder port map (schalter=>s, led=>lx2, aktiv=>k2);
    P3: led_coder port map (schalter=>s, led=>lx3, aktiv=>k3);
    P4: led_coder port map (schalter=>s, led=>lx4, aktiv=>k4);

end struct;


Aber ob dies so die beste Lösung ist bin ich mir garnicht sicher....
hat jemand einen besseren vorschlag... am besten in Source form ?

Danke