PS: sowas muss man nicht wissen, man findet es bei GOOGLE:
Time conversions
When writing testbenches, VHDL users may be forced to convert between
time and abstract numeric types (integer and real). The simplest
conversion is from integer to time:
-- Time_value := Int_value * Time_unit;
timeout := intmax * 1 ns;
Conversion from real to time requires additional typecast (type
conversion):
-- Time_value := integer(Real_value) * Time_unit;
timeout := integer(realmax) * 1 ns;
(Please note that if the real value has fractional part that we want to
preserve, we have to rescale the value and adjust time unit
appropriately.)
Conversions in the opposite direction are more difficult because they
require division operation. In many cases this operation can be executed
without any problems, but quite unexpectedly it can trigger division by
zero or overflow problems.
The first stage of converting time value to abstract value is unit
stripping, which requires division of time value by time unit. This
operation yields integer value that can be typecasted to real and
rescaled if needed:
Int_pico := curr_time / 1 ns * 1000;
Real_pico := real(curr_time / 1 ns) * 1000.0;
What happens if we have simulation resolution set to a value larger than
the divisor used in the conversion? Of course the divisor will be
rounded down to zero, which will trigger ‘division by zero’ error and
termination of simulation.
What happens if the time value (in the divisor units) is greater than
231-1 (e.g. curr_time = 3 sec in our sample code above)? Since the
division result is out of range that integers can handle, we will
experience overflow. It does not necessarily mean termination of
simulation, but incorrect conversion (most significant bit of the
division result treated as the sign bit of the integer value).