1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_ARITH.ALL;
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4 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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5 |
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6 |
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7 | entity toplevel is
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8 |
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9 | Port (
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10 | -- global Control Signals
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11 | clk: in std_logic; -- Clock
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12 | VALID: in std_logic;
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13 | rstn: in std_logic
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14 | -- Command Control Signals
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15 | );
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16 | end toplevel;
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17 |
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18 | architecture Behavioral of toplevel is
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19 |
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20 |
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21 | component toplevel_decode
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22 |
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23 | Port (
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24 | -- global Control Signals
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25 | clk: in std_logic; -- Clock
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26 | rstn: in std_logic;
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27 | ADDR: out std_logic_vector(3 downto 0);
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28 | HDATA: inout std_logic_vector(15 downto 0);
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29 | JDATA: out std_logic_vector(7 downto 0);
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30 | IRQ: in std_logic;
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31 | VALID: in std_logic;
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32 | HOLD: inout std_logic:= '0';
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33 | RAM_ACK: out std_logic;
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34 | ACK: in std_logic;
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35 | RD,WE,CS: out std_logic:= '0';
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36 | send_data : in STD_LOGIC;
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37 | received_data : out STD_LOGIC;
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38 | data_line: in STD_LOGIC_VECTOR(15 downto 0);
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39 | -- Command Control Signals
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40 | clk_pin: out std_logic
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41 | );
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42 | end component;
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43 |
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44 | component toplevel_encode
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45 | Port (
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46 | -- global Control Signals
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47 | clk: in std_logic; -- Clock
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48 | rstn: in std_logic;
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49 | ADDR: out std_logic_vector(3 downto 0);
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50 | HDATA: inout std_logic_vector(15 downto 0);
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51 | IRQ: in std_logic;
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52 | VALID: in std_logic;
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53 | HOLD: inout std_logic:= '0';
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54 | ACK: in std_logic;
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55 | RAM_ACK: in std_logic;
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56 | RD,WE,CS: out std_logic:= '0';
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57 | received_data : in STD_LOGIC;
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58 | send_data : out STD_LOGIC;
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59 | data_line : out STD_LOGIC_VECTOR(15 downto 0)
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60 | -- Command Control Signals
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61 | );
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62 | end component;
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63 |
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64 | SIGNAL s_RAM_ACK: std_logic;
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65 | SIGNAL s_send_data : STD_LOGIC;
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66 | SIGNAL s_received_data : STD_LOGIC;
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67 | SIGNAL s_data_line: STD_LOGIC_VECTOR(15 downto 0);
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68 | SIGNAL s_ADDR1: std_logic_vector(3 downto 0);
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69 | SIGNAL s_HDATA1: std_logic_vector(15 downto 0);
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70 | SIGNAL s_JDATA1: std_logic_vector(7 downto 0);
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71 | SIGNAL s_IRQ1: std_logic;
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72 | --SIGNAL s_VALID1: std_logic;
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73 | SIGNAL s_HOLD1: std_logic:= '0';
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74 | SIGNAL s_RAM_ACK1: std_logic;
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75 | SIGNAL s_ACK1: std_logic;
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76 | SIGNAL s_RD1,s_WE1,s_CS1: std_logic:= '0';
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77 | SIGNAL s_ADDR2: std_logic_vector(3 downto 0);
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78 | SIGNAL s_HDATA2: std_logic_vector(15 downto 0);
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79 | SIGNAL s_JDATA2: std_logic_vector(7 downto 0);
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80 | SIGNAL s_IRQ2: std_logic;
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81 | --SIGNAL s_VALID2: std_logic;
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82 | SIGNAL s_HOLD2: std_logic:= '0';
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83 | SIGNAL s_RAM_ACK2: std_logic;
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84 | SIGNAL s_ACK2: std_logic;
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85 | SIGNAL s_RD2,s_WE2,s_CS2: std_logic:= '0';
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86 |
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87 | begin
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88 |
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89 | component1: toplevel_decode
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90 |
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91 | port map(
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92 | clk => clk,
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93 | rstn => rstn,
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94 | RAM_ACK => s_RAM_ACK,
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95 | send_data => s_send_data,
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96 | received_data => s_received_data,
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97 | data_line => s_data_line,
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98 | ADDR => s_ADDR1,
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99 | HDATA => s_HDATA1,
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100 | JDATA => s_JDATA1,
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101 | IRQ => s_IRQ1,
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102 | -- VALID => s_VALID1,
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103 | VALID => VALID,
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104 | HOLD=> s_HOLD1,
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105 | ACK => s_ACK1,
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106 | RD => s_RD1,
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107 | WE => s_WE1,
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108 | CS => s_CS1
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109 |
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110 | );
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111 |
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112 | component2: toplevel_encode
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113 |
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114 | port map(
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115 | clk => clk,
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116 | rstn => rstn,
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117 | RAM_ACK =>s_RAM_ACK,
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118 | send_data => s_send_data,
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119 | received_data => s_received_data,
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120 | data_line => s_data_line,
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121 | ADDR => s_ADDR2,
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122 | HDATA => s_HDATA2,
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123 | IRQ => s_IRQ2,
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124 | -- VALID => s_VALID2,
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125 | VALID => VALID,
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126 | HOLD=> s_HOLD2,
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127 | ACK => s_ACK2,
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128 | RD => s_RD2,
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129 | WE => s_WE2,
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130 | CS => s_CS2
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131 | );
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132 | end Behavioral;
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