1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_unsigned.all;
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4 | use ieee.std_logic_arith.all;
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5 |
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6 |
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7 | entity uart is
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8 |
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9 | port (
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10 | clk : in std_logic;
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11 | reset : in std_logic;
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12 | seriell_in : in std_logic;
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13 | seriell_out : out std_logic_vector(7 downto 0) := (others => '0');
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14 | seriell_ctr_out : out std_logic := '0';
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15 | test_out : out std_logic_vector(7 downto 0):= (others => '0'));
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16 |
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17 | end uart;
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18 |
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19 |
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20 | architecture rtl of uart is
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21 |
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22 | --type and signal for the finit state machine
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23 | type t_state is (IDLE, START, DATS, PARITY, STOP);
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24 | signal presentstate : t_state;
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25 | signal nextstate : t_state;
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26 |
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27 | --Signal for the prescaler
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28 | signal precount : std_logic := '0';
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29 |
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30 | --Signal for puffering the input
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31 | signal mem_input : std_logic_vector(7 downto 0) := (others => '0');
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32 |
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33 | --constant for the baudrate
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34 | constant baudrate : std_logic_vector(5 downto 0) := conv_std_logic_vector(13,6);--baudrate = 8*460,8kBit/s
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35 |
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36 | begin -- rtl
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37 |
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38 | -- purpose: Prescaler for the uart
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39 | -- type : sequential
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40 | -- inputs : clk48, reset_n
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41 | -- outputs: precount
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42 | Prescaler: process (clk, reset)
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43 | variable count : std_logic_vector(5 downto 0) := (others => '0');
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44 | begin -- process Prescaler
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45 | if reset = '0' then -- asynchronous reset (active low)
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46 | count := (others => '0');
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47 | presentstate <= IDLE;
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48 | elsif clk'event and clk = '1' then -- rising clock edge
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49 | presentstate <= nextstate; -- set the presentstate to the nextstate
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50 | precount <= '0'; -- reset of the variable precount
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51 | count := count + 1;
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52 | if count = baudrate then
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53 | count := (others => '0');
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54 | precount <= '1'; --set of the variable precount
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55 | end if;
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56 |
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57 | end if;
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58 | end process Prescaler;
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59 |
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60 |
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61 | -- purpose: Sequential Process for the fsm
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62 | -- type : sequential
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63 | -- inputs : clk48, reset_n
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64 | -- outputs: presentstate
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65 | seqfsm2: process (clk, reset)
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66 |
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67 | variable count : std_logic_vector(3 downto 0) := (others => '0');
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68 | variable dat1 : std_logic_vector(2 downto 0) := (others => '0');
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69 | variable dat0 : std_logic_vector(2 downto 0) := (others => '1');
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70 | variable pos : integer range 0 to 8 := 0;
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71 |
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72 | begin -- process seqfsm2
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73 | if reset = '0' then -- asynchronous reset (active low)
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74 |
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75 | elsif clk'event and clk = '1' then -- rising clock edge
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76 | seriell_ctr_out <= '0';
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77 | if precount = '1' then
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78 | case presentstate is
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79 | -------------------------------------------------------------------------------
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80 | -- IDLE State
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81 | -------------------------------------------------------------------------------
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82 | when IDLE =>
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83 | mem_input <= (others => '0');
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84 | if seriell_in = '0' then -- if seriell_in = 0 the receiving starts
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85 | nextstate <= START;
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86 | end if;
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87 | -------------------------------------------------------------------
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88 | -- START State
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89 | -------------------------------------------------------------------
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90 | when START =>
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91 | pos := 0;
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92 | if seriell_in = '0' then
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93 | count := count + 1;
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94 | if count = conv_std_logic_vector(7,4) then -- when there were 8 zeros the startbit is finished
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95 | nextstate <= DATS;
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96 | dat1 := (others => '0') ;
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97 | dat0 := (others => '1');
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98 | count := (others => '0');
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99 | end if;
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100 | else
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101 | nextstate <= IDLE; -- when there is a error bei the startbis change back to IDLE Mode
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102 | end if;
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103 | ---------------------------------------------------------------------
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104 | -- DATS State
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105 | ---------------------------------------------------------------------
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106 | when DATS =>
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107 | if seriell_in = '0' then
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108 | dat0 := dat0 - 1;
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109 | count := count + 1;
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110 | end if;
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111 | if seriell_in = '1' then
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112 | dat1 := dat1 + 1;
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113 | count := count + 1;
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114 | end if;
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115 |
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116 | if count = conv_std_logic_vector(5,4) and dat1 = conv_std_logic_vector(5,3) then
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117 | mem_input(pos) <= '1'; --when ther were five times a one the Bitis set to 1
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118 | end if;
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119 | if count = conv_std_logic_vector(5,4) and dat0 = conv_std_logic_vector(2,3) then
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120 | mem_input(pos) <= '0'; --when there were five times a zero the Bit is set to 0
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121 | end if;
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122 |
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123 | if count = conv_std_logic_vector(8,4) then
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124 | pos := pos + 1;
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125 | dat1 := (others => '0');
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126 | dat0 := (others => '1');
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127 | count := (others => '0');
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128 | if pos = 8 then -- if 8 Bits are received he change to the STOP State
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129 | nextstate <= PARITY;
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130 | end if;
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131 | end if;
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132 | ---------------------------------------------------------------------
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133 | -- PARITY State
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134 | ---------------------------------------------------------------------
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135 | when PARITY =>
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136 | --In this state you have the possibility to control the message
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137 | --with the parity bit.
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138 | count := count + 1;
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139 | if count = conv_std_logic_vector(8,4) then --if he received the Stopbit he change to the IDLE State
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140 | nextstate <= STOP;
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141 | count := (others => '0');
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142 | end if;
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143 | ---------------------------------------------------------------------
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144 | -- STOP State
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145 | ---------------------------------------------------------------------
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146 | when STOP => -- STOP State
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147 | if seriell_in = '1' then
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148 | count := count + 1;
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149 | if count = conv_std_logic_vector(8,4) then --if he received the Stopbit he change to the IDLE State
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150 | nextstate <= IDLE;
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151 | count := (others => '0');
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152 | dat1 := (others => '0');
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153 | dat0 := (others => '1');
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154 | seriell_out <= mem_input;
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155 | test_out <= mem_input;
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156 | seriell_ctr_out <= '1';
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157 | end if;
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158 | end if;
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159 | when others => nextstate <= IDLE; --if there is an error the fsm go
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160 | --back to the IDLE state
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161 | end case;
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162 | end if;
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163 | end if;
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164 | end process seqfsm2;
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165 |
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166 |
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167 | end rtl;
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