Forum: Digitale Signalverarbeitung / DSP / Machine Learning Initialisierung EZ-KIT 21369


von André (Gast)


Lesenswert?

Hallo...

Ich entwickle derzeit einen Signalverarbeitungsstrecke im Audiobereich 
auf dem Eval-Board EZ-KIT 21369 von AD.
Unabhängig davon möchte ich die Wandler später auf eine fs=96khz setzen.
Meine Frage betrifft also die Initialisierung des Codecs AD1835a(ADC und 
DAC).

Erstmal der QuellCode aus dem Example Talkthrough, welches den Eingang 
unmodifiziert über die Wandler und SPORTS an die Ausgang routet:

INIT des Codecs
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#include <def21369.h>
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#include "ad1835.h"
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.global _init1835viaSPI;
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//===============================================================
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.section/dm seg_dmda;
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.var spi_semaphore;
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.var config_tx_buf[]=          // Buffer of configuration data
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            WR | DACCTRL1 | DACI2S | DAC24BIT | DACFS48,
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            WR | DACCTRL2, // e.g.: | DACMUTE_R1 | DACMUTE_L2,
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            WR | DACVOL_L1 | DACVOL_MAX,
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            WR | DACVOL_R1 | DACVOL_MAX,
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            WR | DACVOL_L2 | DACVOL_MAX,
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            WR | DACVOL_R2 | DACVOL_MAX,
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            WR | DACVOL_L3 | DACVOL_MAX,
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            WR | DACVOL_R3 | DACVOL_MAX,
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            WR | DACVOL_L4 | DACVOL_MAX,
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            WR | DACVOL_R4 | DACVOL_MAX,
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            WR | ADCCTRL1 | ADCFS48,
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            WR | ADCCTRL2 | ADCI2S | ADC24BIT,
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            WR | ADCCTRL3 | IMCLKx2 | PEAKRDEN;
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//===============================================================
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.section/pm seg_pmco;
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_init1835viaSPI:
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    //--------------------------
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    // Clear SPTFLG and SPICTL regs to start
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    r0 = 0;
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    dm(SPICTL)=r0;
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    dm(SPIFLG)=r0;
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    //---------------------------------------------------------
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    // Writing TXFLSH and RXFLSH bits in SPICTL clear the SPI
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    // transmit and receive FIFOs, respectively.
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    r0 = dm(SPICTL);
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    r1 = (TXFLSH | RXFLSH );
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    r0 = r0 OR r1;
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    dm(SPICTL)=r0;
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    //----------------------------
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    // Setup the baud rate to 500 KHz
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    r0 = 100;
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    dm(SPIBAUD) = r0;
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    //--------------------------------------------
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    // Set the SPIFLG register to FLAG3 (0xF708)
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    r0 = 0xF708;
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    dm(SPIFLG) = r0;
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    //------------------------------------------------------
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    // Now set the SPI control register
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    r0 = (SPIEN |   // enable the port
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          SPIMS |   // set SHARC as SPI master
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          MSBF |    // send MSB first
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          WL16 |    // word length = 16 bits
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          TIMOD1);  // Initialize SPI port to begin
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                    // transmitting when DMA is enabled
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    dm(SPICTL) = r0;
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    //-------------------------------------------
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    // Set up DAG registers to transmit via SPI
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    i4 = config_tx_buf;
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    m4 = 1;
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    //------------------------------
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    // Set up loop to transmit data
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    lcntr = LENGTH(config_tx_buf), do word_sent until lce;
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        // Send a word
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        r0=dm(i4,m4);
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        dm(TXSPI)=r0;
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        // Wait until "SPI transfer complete" status bit
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        //   in SPISTAT (SPIF) indicates that we can send more
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        do checkIfTXisDone until TF;
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            ustat3 = dm(SPISTAT);
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            BIT TST ustat3 SPIF;
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        checkIfTXisDone:
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        nop;
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        // Wait an extra 100 cycles to meet the timing
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        //   requirements of the AD1835A
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        lcntr = 100, do pauseFor1835 until lce;
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        pauseFor1835:
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        nop;
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    word_sent:
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    nop;
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/*
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    //-----------------------------------------
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    // Flush SPI buffers after initialization
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    //   You may want to do this before sending
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    //   other SPI commands to guarantee that
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    //   you have not accidentally left data in
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    //   the transmit or receive FIFOs.
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    r0 = dm(SPICTL);
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    r1 = (TXFLSH | RXFLSH );
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    r0 = r0 OR r1;
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    dm(SPICTL)=r0;
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*/
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_init1835viaSPI.end:
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    rts;

Headerfile
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#ifndef _AD1835_H_
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#define _AD1835_H_
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//
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//  AD1835.h
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//
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//  Configuration values for the AD1835A codec
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//
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#define DACCTRL1     (0x0000)  // DAC control register 1    (R/W)
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#define DACCTRL2     (0x1000)  // DAC control register 2    (R/W)
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#define DACVOL_L1   (0x2000)  // DAC volume - left 1       (R/W)
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#define DACVOL_R1   (0x3000)  // DAC volume - right 1      (R/W)
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#define DACVOL_L2   (0x4000)  // DAC volume - left 2       (R/W)
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#define DACVOL_R2   (0x5000)  // DAC volume - right 2      (R/W)
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#define DACVOL_L3   (0x6000)  // DAC volume - left 3       (R/W)
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#define DACVOL_R3   (0x7000)  // DAC volume - right 3      (R/W)
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#define DACVOL_L4   (0x8000)  // DAC volume - left 4       (R/W)
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#define DACVOL_R4   (0x9000)  // DAC volume - right 4      (R/W)
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#define ADCPEAKL     (0xA000)  // ADC left peak              (R)
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#define ADCPEAKR     (0xB000)  // ADC right peak             (R)
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#define ADCCTRL1     (0xC000)  // ADC control 1             (R/W)
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#define ADCCTRL2     (0xD000)  // ADC control 2             (R/W)
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#define ADCCTRL3     (0xE000)  // ADC control 3             (R/W)
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#define RD           (0x0800)
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#define WR           (0x0000)  // Write to register
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// DAC control register 1
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#define DEEMPH44_1   (0x0100)  // Deemphasis filter for 44.1 KHz
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#define DEEMPH32     (0x0200)  // Deemphasis filter for 32.0 KHz
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#define DEEMPH48     (0x0300)  // Deemphasis filter for 48.0 KHz
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#define DACI2S       (0x0000)  // DAC receives I2S format
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#define DACRJ        (0x0020)  // DAC receives I2S format
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#define DACDSP       (0x0040)  // DAC receives I2S format
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#define DACLJ        (0x0060)  // DAC receives I2S format
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#define DACPACK256   (0x0080)  // DAC receives I2S format
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#define DAC24BIT     (0x0000)  // 24-bit output word length
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#define DAC20BIT     (0x0008)  // 20-bit output word length
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#define DAC16BIT     (0x0010)  // 16-bit output word length
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#define DACPOWERDN   (0x0004)  // DAC into power-down mode
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#define DACFS48      (0x0000)  // Sample rate = 48 KHz (x8)
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#define DACFS96      (0x0001)  // Sample rate = 96 KHz (x4)
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#define DACFS192     (0x0002)  // Sample rate = 192 KHz (x2)
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// DAC control register 2
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#define DACREPLICATE  (0x0100)  // Replicate output of DAC 1/2 on 3/4, 5/6 & 7/8
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#define DACMUTE_R4    (0x0080)  // Mute DAC output channel (clear to un-mute)
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#define DACMUTE_L4    (0x0040)  // Mute DAC output channel (clear to un-mute)
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#define DACMUTE_R3    (0x0020)  // Mute DAC output channel (clear to un-mute)
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#define DACMUTE_L3    (0x0010)  // Mute DAC output channel (clear to un-mute)
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#define DACMUTE_R2    (0x0008)  // Mute DAC output channel (clear to un-mute)
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#define DACMUTE_L2    (0x0004)  // Mute DAC output channel (clear to un-mute)
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#define DACMUTE_R1    (0x0002)  // Mute DAC output channel (clear to un-mute)
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#define DACMUTE_L1    (0x0001)  // Mute DAC output channel (clear to un-mute)
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//-------------------------------------------------------------------------------
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//DAC Volume Control - 10-bit granularity (1024 levels)
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#define DACVOL_MIN      (0x000)
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#define DACVOL_LOW      (0X100)
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#define DACVOL_MED      (0X200)
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#define DACVOL_HI       (0X300)
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#define DACVOL_MAX      (0x3FF)
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#define DACVOL_MASK     (0x3FF)  // Volume in dB is in 10 LSBs
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                                 //   3FF = 0 dBFS = 1023/1023
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                                 //   3FE = -0.01 dBFS = 1022/1023
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                                 //      ...
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                                 //   002 = -50.7 dBFS = 3/1023
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                                 //   001 = -54.2 dBFS = 2/1023
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//-------------------------------------------------------------------------------
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//  ADC Control 1
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#define ADCHPF     (0x0100)  // High pass filter (AC-coupled)
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#define ADCPOWERDN (0x0080)  // DAC into power-down mode
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#define ADCFS48    (0x0000)  // Sample rate = 48 KHz
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#define ADCFS96    (0x0001)  // Sample rate = 96 KHz
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//-------------------------------------------------------------------------------
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//  ADC Control 2
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#define AUXSLAVE   (0x0000)  // Aux input is in slave mode
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#define AUXMASTER  (0x0200)  // Aux input is in master mode
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#define ADCI2S     (0x0000)  // ADC transmits in I2S format
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#define ADCRJ      (0x0040)  // ADC transmits in right-justified format
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#define ADCDSP     (0x0080)  // ADC transmits in DSP (TDM) format
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#define ADCLJ      (0x00C0)  // ADC transmits in left-justified format
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#define ADCPACK256 (0x0100)  // ADC transmits in packed 256 format
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#define ADCAUX256  (0x0180)  // ADC transmits in packed 128 format
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#define ADC24BIT   (0x0000)  // 24-bit output word length
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#define ADC20BIT   (0x0010)  // 20-bit output word length
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#define ADC16BIT   (0x0020)  // 16-bit output word length
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#define ADCMUTER   (0x0002)  // Mute right channel from ADC
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#define ADCMUTEL   (0x0001)  // Mute right channel from ADC
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//-------------------------------------------------------------------------------
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//  ADC Control 3
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#define IMCLKx2    (0x0000)  // Internal MCLK = external MCLK x 2
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#define IMCLKx1    (0x0080)  // Internal MCLK = external MCLK
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#define IMCLKx23   (0x0100)  // Internal MCLK = external MCLK x 2/3
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#define PEAKRDEN   (0x0020)  // Enable reads of peak ADC levels
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#define PEAKLEVELMASK  (0x003F)  // Six significant bit of level
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                  // 000000 = 0dBFS, -1dB/LSB
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#endif



Einfachheitshalber hab ich ganz oben in der Initialisierung die ODER- 
Verknüpfungen von DACFS48 und ADCFS48 durch DACFS96 und ADCFS96 ersetzt. 
Aber das scheint dann doch nicht so einfach zu sein. Vielleicht hab ich 
ja noch einen grundlegende Sache nicht beachtet. Aber ich weiß da 
irgendwie nicht weiter.
Wenn jemand Erfahrungen mit dem speziellen Codec oder idealerweise mit 
dem EZ-KIT 21369 hat und mir helfen könnte würde ich mich freuen.

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