1 | #ifndef _AD1835_H_
|
2 | #define _AD1835_H_
|
3 |
|
4 | //
|
5 | // AD1835.h
|
6 | //
|
7 | // Configuration values for the AD1835A codec
|
8 | //
|
9 |
|
10 | #define DACCTRL1 (0x0000) // DAC control register 1 (R/W)
|
11 | #define DACCTRL2 (0x1000) // DAC control register 2 (R/W)
|
12 | #define DACVOL_L1 (0x2000) // DAC volume - left 1 (R/W)
|
13 | #define DACVOL_R1 (0x3000) // DAC volume - right 1 (R/W)
|
14 | #define DACVOL_L2 (0x4000) // DAC volume - left 2 (R/W)
|
15 | #define DACVOL_R2 (0x5000) // DAC volume - right 2 (R/W)
|
16 | #define DACVOL_L3 (0x6000) // DAC volume - left 3 (R/W)
|
17 | #define DACVOL_R3 (0x7000) // DAC volume - right 3 (R/W)
|
18 | #define DACVOL_L4 (0x8000) // DAC volume - left 4 (R/W)
|
19 | #define DACVOL_R4 (0x9000) // DAC volume - right 4 (R/W)
|
20 | #define ADCPEAKL (0xA000) // ADC left peak (R)
|
21 | #define ADCPEAKR (0xB000) // ADC right peak (R)
|
22 | #define ADCCTRL1 (0xC000) // ADC control 1 (R/W)
|
23 | #define ADCCTRL2 (0xD000) // ADC control 2 (R/W)
|
24 | #define ADCCTRL3 (0xE000) // ADC control 3 (R/W)
|
25 |
|
26 | #define RD (0x0800)
|
27 | #define WR (0x0000) // Write to register
|
28 |
|
29 |
|
30 | // DAC control register 1
|
31 | #define DEEMPH44_1 (0x0100) // Deemphasis filter for 44.1 KHz
|
32 | #define DEEMPH32 (0x0200) // Deemphasis filter for 32.0 KHz
|
33 | #define DEEMPH48 (0x0300) // Deemphasis filter for 48.0 KHz
|
34 |
|
35 | #define DACI2S (0x0000) // DAC receives I2S format
|
36 | #define DACRJ (0x0020) // DAC receives I2S format
|
37 | #define DACDSP (0x0040) // DAC receives I2S format
|
38 | #define DACLJ (0x0060) // DAC receives I2S format
|
39 | #define DACPACK256 (0x0080) // DAC receives I2S format
|
40 |
|
41 | #define DAC24BIT (0x0000) // 24-bit output word length
|
42 | #define DAC20BIT (0x0008) // 20-bit output word length
|
43 | #define DAC16BIT (0x0010) // 16-bit output word length
|
44 |
|
45 | #define DACPOWERDN (0x0004) // DAC into power-down mode
|
46 |
|
47 | #define DACFS48 (0x0000) // Sample rate = 48 KHz (x8)
|
48 | #define DACFS96 (0x0001) // Sample rate = 96 KHz (x4)
|
49 | #define DACFS192 (0x0002) // Sample rate = 192 KHz (x2)
|
50 |
|
51 |
|
52 | // DAC control register 2
|
53 |
|
54 | #define DACREPLICATE (0x0100) // Replicate output of DAC 1/2 on 3/4, 5/6 & 7/8
|
55 | #define DACMUTE_R4 (0x0080) // Mute DAC output channel (clear to un-mute)
|
56 | #define DACMUTE_L4 (0x0040) // Mute DAC output channel (clear to un-mute)
|
57 | #define DACMUTE_R3 (0x0020) // Mute DAC output channel (clear to un-mute)
|
58 | #define DACMUTE_L3 (0x0010) // Mute DAC output channel (clear to un-mute)
|
59 | #define DACMUTE_R2 (0x0008) // Mute DAC output channel (clear to un-mute)
|
60 | #define DACMUTE_L2 (0x0004) // Mute DAC output channel (clear to un-mute)
|
61 | #define DACMUTE_R1 (0x0002) // Mute DAC output channel (clear to un-mute)
|
62 | #define DACMUTE_L1 (0x0001) // Mute DAC output channel (clear to un-mute)
|
63 |
|
64 |
|
65 | //-------------------------------------------------------------------------------
|
66 | //DAC Volume Control - 10-bit granularity (1024 levels)
|
67 | #define DACVOL_MIN (0x000)
|
68 | #define DACVOL_LOW (0X100)
|
69 | #define DACVOL_MED (0X200)
|
70 | #define DACVOL_HI (0X300)
|
71 | #define DACVOL_MAX (0x3FF)
|
72 | #define DACVOL_MASK (0x3FF) // Volume in dB is in 10 LSBs
|
73 | // 3FF = 0 dBFS = 1023/1023
|
74 | // 3FE = -0.01 dBFS = 1022/1023
|
75 | // ...
|
76 | // 002 = -50.7 dBFS = 3/1023
|
77 | // 001 = -54.2 dBFS = 2/1023
|
78 |
|
79 | //-------------------------------------------------------------------------------
|
80 | // ADC Control 1
|
81 |
|
82 | #define ADCHPF (0x0100) // High pass filter (AC-coupled)
|
83 | #define ADCPOWERDN (0x0080) // DAC into power-down mode
|
84 | #define ADCFS48 (0x0000) // Sample rate = 48 KHz
|
85 | #define ADCFS96 (0x0001) // Sample rate = 96 KHz
|
86 |
|
87 | //-------------------------------------------------------------------------------
|
88 | // ADC Control 2
|
89 |
|
90 | #define AUXSLAVE (0x0000) // Aux input is in slave mode
|
91 | #define AUXMASTER (0x0200) // Aux input is in master mode
|
92 |
|
93 | #define ADCI2S (0x0000) // ADC transmits in I2S format
|
94 | #define ADCRJ (0x0040) // ADC transmits in right-justified format
|
95 | #define ADCDSP (0x0080) // ADC transmits in DSP (TDM) format
|
96 | #define ADCLJ (0x00C0) // ADC transmits in left-justified format
|
97 | #define ADCPACK256 (0x0100) // ADC transmits in packed 256 format
|
98 | #define ADCAUX256 (0x0180) // ADC transmits in packed 128 format
|
99 |
|
100 | #define ADC24BIT (0x0000) // 24-bit output word length
|
101 | #define ADC20BIT (0x0010) // 20-bit output word length
|
102 | #define ADC16BIT (0x0020) // 16-bit output word length
|
103 |
|
104 | #define ADCMUTER (0x0002) // Mute right channel from ADC
|
105 | #define ADCMUTEL (0x0001) // Mute right channel from ADC
|
106 |
|
107 | //-------------------------------------------------------------------------------
|
108 | // ADC Control 3
|
109 |
|
110 | #define IMCLKx2 (0x0000) // Internal MCLK = external MCLK x 2
|
111 | #define IMCLKx1 (0x0080) // Internal MCLK = external MCLK
|
112 | #define IMCLKx23 (0x0100) // Internal MCLK = external MCLK x 2/3
|
113 |
|
114 | #define PEAKRDEN (0x0020) // Enable reads of peak ADC levels
|
115 | #define PEAKLEVELMASK (0x003F) // Six significant bit of level
|
116 | // 000000 = 0dBFS, -1dB/LSB
|
117 |
|
118 | #endif
|