Hi
es scheint als würde da schon was beim VHDL model schiefgehen.
////////////////////////////////////////////////////////////////////////
///
`timescale 1ns / 1ps
module FTRSE_MXILINX_ownshem(C,
CE,
R,
S,
T,
Q);
input C;
input CE;
input R;
input S;
input T;
output Q;
wire CE_S;
wire D_S;
wire TQ;
XOR2 I_36_32 (.I0(T),
.I1(Q),
.O(TQ));
FDRE I_36_35 (.C(C),
.CE(CE_S),
.D(D_S),
.R(R),
.Q(Q));
// synthesis attribute RLOC of I_36_35 is "X0Y0"
defparam I_36_35.INIT = 1'b0;
OR2 I_36_73 (.I0(S),
.I1(TQ),
.O(D_S));
OR2 I_36_77 (.I0(CE),
.I1(S),
.O(CE_S));
endmodule
`timescale 1ns / 1ps
module CB2RE_MXILINX_ownshem(C,
CE,
R,
CEO,
Q0,
Q1,
TC);
input C;
input CE;
input R;
output CEO;
output Q0;
output Q1;
output TC;
wire XLXN_1;
wire XLXN_2;
FTRSE_MXILINX_ownshem I_Q0 (.C(C),
.CE(CE),
.R(R),
.S(XLXN_2),
.T(XLXN_1),
.Q(Q0));
// synthesis attribute HU_SET of I_Q0 is "I_Q0_0"
FTRSE_MXILINX_ownshem I_Q1 (.C(C),
.CE(CE),
.R(R),
.S(XLXN_2),
.T(Q0),
.Q(Q1));
// synthesis attribute HU_SET of I_Q1 is "I_Q1_1"
AND2 I_36_37 (.I0(Q1),
.I1(Q0),
.O(TC));
VCC I_36_47 (.P(XLXN_1));
GND I_36_54 (.G(XLXN_2));
AND2 I_36_55 (.I0(CE),
.I1(TC),
.O(CEO));
endmodule
`timescale 1ns / 1ps
module ownshem(in1,
in2,
out1,
out2,
useless1,
useless2,
useless3);
input in1;
input in2;
output out1;
output out2;
output useless1;
output useless2;
output useless3;
wire gnd1;
wire vcc1;
AND2 XLXI_1 (.I0(in2),
.I1(in1),
.O(out1));
CB2RE_MXILINX_ownshem XLXI_2 (.C(out1),
.CE(vcc1),
.R(gnd1),
.CEO(useless2),
.Q0(out2),
.Q1(useless1),
.TC(useless3));
// synthesis attribute HU_SET of XLXI_2 is "XLXI_2_2"
VCC XLXI_3 (.P(vcc1));
GND XLXI_4 (.G(gnd1));
endmodule
Ideen?
Tobi
schematics.png
(34 KB)
