1 | // The following functions must be write in ARM mode this function called directly
|
2 | // by exception vector
|
3 | extern void AT91F_Spurious_handler(void);
|
4 | extern void AT91F_Default_IRQ_handler(void);
|
5 | extern void AT91F_Default_FIQ_handler(void);
|
6 |
|
7 | //*----------------------------------------------------------------------------
|
8 | //* \fn AT91F_LowLevelInit
|
9 | //* \brief This function performs very low level HW initialization
|
10 | //* this function can be use a Stack, depending the compilation
|
11 | //* optimization mode
|
12 | //*----------------------------------------------------------------------------
|
13 | void AT91F_LowLevelInit( void) @ "ICODE"
|
14 | {
|
15 | int i;
|
16 | AT91PS_PMC pPMC = AT91C_BASE_PMC;
|
17 | //* Set Flash Waite sate
|
18 | // Single Cycle Access at Up to 30 MHz, or 40
|
19 | // if MCK = 47923200 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
|
20 | AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(48 <<16)) | AT91C_MC_FWS_1FWS ;
|
21 |
|
22 | //* Watchdog Disable
|
23 | AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
|
24 |
|
25 | //* Set MCK at 47 923 200
|
26 | // 1 Enabling the Main Oscillator:
|
27 | // SCK = 1/32768 = 30.51 uSecond
|
28 | // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
|
29 | pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x0 <<8) | AT91C_CKGR_MOSCEN ));
|
30 | // Wait the startup time
|
31 | while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
|
32 | // 2 Checking the Main Oscillator Frequency (Optional)
|
33 | // 3 Setting PLL and divider:
|
34 | // - div by 5 Fin = 3,6864 =(18,432 / 5)
|
35 | // - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
|
36 | // for 96 MHz the erroe is 0.16%
|
37 | // Field out NOT USED = 0
|
38 | // PLLCOUNT pll startup time estimate at : 0.844 ms
|
39 | // PLLCOUNT 28 = 0.000844 /(1/32768)
|
40 | pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x01) |
|
41 | (AT91C_CKGR_PLLCOUNT & (28<<8)) |
|
42 | (AT91C_CKGR_MUL & (25<<16)));
|
43 |
|
44 | // Wait the startup time
|
45 | while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
|
46 | while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
|
47 | // 4. Selection of Master Clock and Processor Clock
|
48 | // select the PLL clock divided by 2
|
49 | pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK ;
|
50 | while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
|
51 |
|
52 | pPMC->PMC_MCKR |= AT91C_PMC_CSS_MAIN_CLK ;
|
53 | while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
|
54 |
|
55 | // Set up the default interrupts handler vectors
|
56 | AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
|
57 | for (i=1;i < 31; i++)
|
58 | {
|
59 | AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
|
60 | }
|
61 | AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
|
62 |
|
63 | }
|