1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_ARITH.ALL;
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4 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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5 |
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6 | entity Displayausgabe is
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7 | port(
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8 | clk : in std_logic;
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9 | enable : in std_logic;
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10 | data6_in : in std_logic_vector(5 downto 0);
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11 | data6_in_sram : in std_logic_vector(5 downto 0);
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12 | red_out1 : out std_logic;
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13 | red_out2 : out std_logic;
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14 | red_out3 : out std_logic;
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15 | red_out4 : out std_logic;
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16 | red_out5 : out std_logic;
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17 | red_out0 : out std_logic;
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18 | green_out1 : out std_logic;
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19 | green_out2 : out std_logic;
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20 | green_out3 : out std_logic;
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21 | green_out4 : out std_logic;
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22 | green_out5 : out std_logic;
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23 | green_out0 : out std_logic;
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24 | blue_out1 : out std_logic;
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25 | blue_out2 : out std_logic;
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26 | blue_out3 : out std_logic;
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27 | blue_out4 : out std_logic;
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28 | blue_out5 : out std_logic;
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29 | blue_out0 : out std_logic;
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30 | pci : out std_logic;
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31 | vctrl : out std_logic;
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32 | dtmg : out std_logic;
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33 | hc_signal : out std_logic_vector(8 downto 0);
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34 | vc_signal : out std_logic_vector(8 downto 0);
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35 | hs_out : out std_logic
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36 | );
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37 |
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38 | end Displayausgabe;
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39 |
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40 | architecture Behavioral of Displayausgabe is
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41 |
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42 | signal horizontal_counter : std_logic_vector (8 downto 0);
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43 | signal vertical_counter : std_logic_vector (8 downto 0);
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44 | signal clkcount : std_logic_vector (3 downto 0);
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45 | signal clkdiv8 : std_logic;
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46 | signal Linelength : std_logic_vector(8 downto 0);
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47 | signal Columlength : std_logic_vector(8 downto 0);
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48 | signal Counter : std_logic_vector(18 downto 0);
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49 |
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50 | begin
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51 |
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52 | process(clk)
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53 |
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54 | begin
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55 |
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56 | if rising_edge(clk) then
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57 |
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58 |
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59 | if (enable = '1' and vertical_counter = "0000000000") then
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60 |
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61 | vctrl <= '0';
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62 | dtmg <= '0';
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63 | hs_out <= '0';
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64 |
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65 | horizontal_counter <= "000000000";
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66 |
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67 |
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68 |
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69 | else
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70 |
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71 | vctrl <= '1';
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72 | Linelength <= "010110001" ; --177
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73 | Columlength <= "010010000"; --144
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74 |
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75 | horizontal_counter <= horizontal_counter+"0000000001";
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76 |
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77 | if (horizontal_counter="100010001") then --273
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78 | horizontal_counter <= "000000000";
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79 | vertical_counter <= vertical_counter + '1';
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80 | end if;
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81 |
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82 | if vertical_counter = "101000111" then -- 327
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83 | vertical_counter <= "000000000";
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84 |
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85 | pci <= '0' ;
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86 | horizontal_counter <= "000000000";
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87 | end if;
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88 |
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89 |
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90 |
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91 |
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92 | if (horizontal_counter > "000000000" )
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93 | and (horizontal_counter < "11111100" ) -- 252
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94 | then
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95 | hs_out <= '1';
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96 | else
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97 | hs_out <= '0';
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98 | end if;
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99 |
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100 |
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101 | vc_signal <= vertical_counter;
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102 |
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103 | if (horizontal_counter > "000000001" )and (horizontal_counter < "011110011" ) then-- zwichen 1 und 243 sing genau 240
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104 |
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105 | dtmg <= '1';
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106 | pci <= '1';
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107 | hc_signal <= horizontal_counter - "000000001"; -- dient zum Ansteuern des Dualport ram für diese
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108 |
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109 | else
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110 | dtmg <= '0';
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111 | pci <= '0';
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112 |
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113 | hc_signal <= "000000000";
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114 | end if;
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115 |
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116 |
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117 | green_out5 <= '0'; -- MSB
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118 | green_out4 <= '0';
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119 | green_out3 <= '0';
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120 | green_out2 <= '0';
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121 | green_out1 <= '0';
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122 | green_out0 <= '0';
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123 |
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124 | blue_out5 <= '0'; -- MSB
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125 | blue_out4 <= '0';
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126 | blue_out3 <= '0';
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127 | blue_out2 <= '0';
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128 | blue_out1 <= '0';
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129 | blue_out0 <= '0';
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130 |
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131 | red_out5 <= '1'; --MSB
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132 | red_out4 <= '0';
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133 | red_out3 <= '1';
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134 | red_out2 <= '0';
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135 | red_out1 <= '1';
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136 | red_out0 <= '0';
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137 |
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138 | end if;
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139 | end if;
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140 | end process;
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141 | end Behavioral;
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