MSP430F2013 - SPI Signalproblem

#include <msp430x20x3.h>

void spi_init(void);

void spi_write(unsigned int, unsigned int);

void wait(unsigned int);

void main(void)

{

  WDTCTL = WDTPW + WDTHOLD;             // Stop watchdog timer

  P1DIR = 0x10;                         // P1.4 output-FSYNC

  spi_init();

  while(1) 

  {

  wait(0x01);

  spi_dds_write(0x21,0x00);     //Send 16 Bit 0x2100

  }

}

void spi_init(void)

{

USICTL0 |= USISWRST;                        // Set USI Reset-Bit for Config

USICTL0 |= USIPE6 + USIPE5 + USIMST + USIOE;  // Ports, SPI master

USICKCTL = USIDIV_1 + USISSEL_2 + USICKPL;    // 400kHz SCLK, CLK idle high

USICTL0 &= ~USISWRST;                         // USI released for operation

}

void spi_write(unsigned int high, unsigned int low)

{

  USISRL = low;                        

  USISRH = high;

  P1OUT &=~ 0x10;        //CS low

  USICNT = 80;  // Counter=16,  16 Bit Operation //Start des Sendevorgangs

  while(!(USIIFG & USICTL1)); //Warten bis Sendevorgang beendet ist

  P1OUT |= 0x10;       //CS high

}

void wait(unsigned int cycles)

{

  volatile unsigned int i;

  for(i=0;i<cycles;i++);

}