Virtex4 DMC ClockIn mit Frequenzen kleiner 19Mhz

[FPGA_Beginner (Gast)]

Hallöchen,

ich hab ein Problem mit den DCMs von Xilinx.
Mein Eingangssignal hat eine Frequenz von 10Mhz und geht über einen 
IBUFG an den DCM_BASE.
Im Virtex4 Datasheet steht nun aber 
("http://www.xilinx.com/support/documentation/data_sheets/ds302.pdf";
,p.38 Table 46), dass mein FPGA (FX20 -11)
am CLKIN (using DLL outputs) mindestens 19Mhz anliegen haben muss. Ich 
habs getestet und es geht auch mit mind. 14 MHz. Bei 13 MHz geht der DCM 
allerdings nicht mehr in Locked über.
Jetzt wirds aber interessant... In der nächsten Zeile der Tabelle, wo 
steht CLKIN (using DFS outputs only), ist eine Frequenzrange von 1 bis 
32 MHz angegeben.
Wie muss ich meinen DCM konfigurieren, damit ich diese niedrigen 
Frequenzen  (10MHz) am ClockIn anlegen kann?

Vielen Dank für Eure Antworten im Vorraus!

Mein Code für V4 xc4vfx20-11ff672:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;


entity Toplevel is
port(
    SysRst_pin    : in std_logic;
    SysRstPressed_pin  : out std_logic;

    ClkIn_pin      : in std_logic;
    Clk0Out_pin    : out std_logic;
    ClkFxOut_pin  : out std_logic;

    ClkLocked_pin : out std_logic
    );
end Toplevel;

architecture Behavioral of Toplevel is
-- Constants
constant Low  : std_logic  := '0';

-- Signals
signal SysRst : std_logic;
signal SysRst_Temp : std_logic;

signal ClkIn : std_logic;

signal Clk0ToBufg : std_logic;
signal BufgToClkfb : std_logic;
signal ClkFXOutToOBUF : std_logic;

signal ClkLocked : std_logic;

-- Constraints
--attribute LOC : string;
--  attribute LOC of DCM_ADV_inst : label is "DCM_ADV_X0Y2";

begin
  --Reset In
  IBUF_SysRst : IBUF
   generic map (
      IBUF_DELAY_VALUE => "0", -- Specify the amount of added input 
delay for buffer, "0"-"16" (Spartan-3E/3A only)
      IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay 
for input register, "AUTO", "0"-"8" (Spartan-3E/3A only)
      IOSTANDARD => "DEFAULT")
   port map (
      O => SysRst_Temp,     -- Buffer output
      I => SysRst_pin      -- Buffer input (connect directly to 
top-level port)
   );

  SysRst <= not(SysRst_Temp);

  -- Clock In
  IBUFG_ClkIn : IBUFG
   generic map (
      IBUF_DELAY_VALUE => "0", -- Specify the amount of added input 
delay for buffer, "0"-"16" (Spartan-3E/3A only)
      IOSTANDARD => "LVCMOS25")
   port map (
      O => ClkIn, -- Clock buffer output
      I => ClkIn_pin  -- Clock buffer input (connect directly to 
top-level port)
   );

   -- DCM_ADV: Digital Clock Manager Circuit
   --          Virtex-4/5
   -- Xilinx HDL Language Template, version 9.2.4i

   DCM_ADV_inst : DCM_BASE
   generic map (
     CLKDV_DIVIDE => 2.0,  -- Divide by: 
1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                            -- 
7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 4,    -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY => 4,  -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2 => FALSE,    -- TRUE/FALSE to enable CLKIN 
divide by two feature
      CLKIN_PERIOD => 100.0,          -- Specify period of input clock 
in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT => "NONE",  -- Specify phase shift mode of 
NONE, FIXED,
                                     -- VARIABLE_POSITIVE, 
VARIABLE_CENTER or DIRECT
      CLK_FEEDBACK => "NONE",  -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry 
TRUE/FALSE
      DCM_PERFORMANCE_MODE => "MAX_RANGE",   -- Can be MAX_SPEED or 
MAX_RANGE
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, 
SYSTEM_SYNCHRONOUS or
                                             --   an integer from 0 to 
15
      DFS_FREQUENCY_MODE => "LOW",    -- HIGH or LOW frequency mode for 
frequency synthesis
      DLL_FREQUENCY_MODE => "LOW",    -- LOW, HIGH, or HIGH_SER 
frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE,  -- Duty cycle correction, TRUE or 
FALSE
      FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to 
be set to X"F0F0"
      PHASE_SHIFT => 0,  -- Amount of fixed phase shift from -255 to 
1023
      STARTUP_WAIT => FALSE)  -- Delay configuration DONE until DCM 
LOCK, TRUE/FALSE
   port map (
      CLK0 => open,--Clk0ToBufg,         -- 0 degree DCM CLK output
      CLK180 => open,     -- 180 degree DCM CLK output
      CLK270 => open,     -- 270 degree DCM CLK output
      CLK2X => open,       -- 2X DCM CLK output
      CLK2X180 => open, -- 2X, 180 degree DCM CLK out
      CLK90 => open,       -- 90 degree DCM CLK output
      CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => ClkFXOutToOBUF,       -- DCM CLK synthesis out (M/D)
      CLKFX180 => open, -- 180 degree CLK synthesis out
      LOCKED => ClkLocked,     -- DCM LOCK status output
      CLKFB => BufgToClkfb,       -- DCM clock feedback
      CLKIN => ClkIn,       -- Clock input (from IBUFG, BUFG or DCM)
      RST => SysRst            -- DCM asynchronous reset input
   );


  -- Clock Feedback Buffer
  BUFG_BufgToClkfb : BUFG
    port map (
      O => BufgToClkfb,       -- Clock buffer output
      I => ClkFXOutToOBUF--Clk0ToBufg        -- Clock buffer input
    );

  -- Clock Out
  OBUF_Clk0Out_pin : OBUF
    generic map (
      DRIVE => 12,
      IOSTANDARD => "LVCMOS25",
      SLEW => "FAST")
    port map (
      O => Clk0Out_pin,     -- Buffer output (connect directly to 
top-level port)
      I => BufgToClkfb      -- Buffer input
   );

  -- ClockDV Out
  OBUF_ClkDvOut_pin : OBUF
    generic map (
      DRIVE => 12,
      IOSTANDARD => "LVCMOS25",
      SLEW => "FAST")
    port map (
      O => ClkFxOut_pin,     -- Buffer output (connect directly to 
top-level port)
      I => ClkFXOutToOBUF      -- Buffer input
   );

  -- DCM Locked Out
  OBUF_ClkLocked_pin : OBUF
    generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
    port map (
      O => ClkLocked_pin,     -- Buffer output (connect directly to 
top-level port)
      I => ClkLocked      -- Buffer input
   );

  -- DCM SysRstPressed Out
  OBUF_SysRstPressed_pin : OBUF
    generic map (
      DRIVE => 12,
      IOSTANDARD => "DEFAULT",
      SLEW => "SLOW")
    port map (
      O => SysRstPressed_pin,     -- Buffer output (connect directly to 
top-level port)
      I => SysRst            -- Buffer input
   );

end Behavioral;

[Matthias F. (flint)]

DLL und DFS ist nicht das selbe, wenn du DLL Ausgänge in der DCM 
verwendest gelten automatisch deren Grenzen. Wenn die DFS-Grenzen gelten 
sollen dürfen auch nur DFS-Ausgänge benutzt werden. Hatte das auch 
schon, das Datenblatt hilft weiter.

[FPGA_Beginner (Gast)]

Alles klaro... ich versuch mal mein Glück...
Danke