Hallo, ich weiß nicht mehr weiter... Ich wollte in VHDL einen Counter schreiben aber beim syntehtisieren (ISE) bekomme ich nur immer '+ can not have such operands in this context'
1 | library IEEE; |
2 | use IEEE.std_logic_1164.all; |
3 | |
4 | entity COUNTER is |
5 | Port ( CLK : In STD_LOGIC; |
6 | ENABLE : In STD_LOGIC; |
7 | MODE : In STD_LOGIC; |
8 | REG_IN : In std_logic_vector (3 downto 0); |
9 | RES : In STD_LOGIC; |
10 | PC_OUT : Out std_logic_vector (3 downto 0) ); |
11 | end COUNTER; |
12 | |
13 | architecture BEHAVIORAL of COUNTER is |
14 | signal pc_state: std_logic_vector (3 downto 0); |
15 | begin
|
16 | |
17 | PC_OUT <= pc_state; |
18 | |
19 | process (clk, RES) |
20 | begin
|
21 | if (RES = '1') then pc_state <= "0000"; -- Reset asynchron |
22 | end if; |
23 | |
24 | if (ENABLE = '1') then |
25 | if (clk='1' and clk'event) then |
26 | if (MODE = '1') then |
27 | pc_state <= REG_IN; |
28 | end if; |
29 | |
30 | if (MODE = '0') then |
31 | if (pc_state="1111") then |
32 | pc_state <= "0000"; -- Overflow |
33 | else
|
34 | pc_state <= pc_state + 1; |
35 | end if; |
36 | end if; |
37 | end if; |
38 | end if; |
39 | end process; |
40 | |
41 | end BEHAVIORAL; |
Weiß jemand warum VHDL den '+' Operator stört? Wolif