Hallo zusammen,
Im Rahmen einer Projektarbeit beschäftige ich mich mit Quartus II.
Mittlerweile kenn ich des Programm ganz gut, nur VHDL bereitet mir
großes Kopfzerbrechen.
Ich wäre deshalb für Tipps zur Lösung für folgendes Problem sehr
dankbar.
Mit dem Programm QFSM ist es möglich aus Zustandsdiagrammen VHDL Code zu
generieren. Der erzeugte Code eines 3-Bit Modulo6 Zählers lässt sich in
Quartus aber nicht compilieren. Es werden zwei Fehlermeldungen
Ausgegeben:
1 | Error (10500): VHDL syntax error at 3BM6Vorw.vhdl(25) near text "3"; expecting an identifier
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2 | Error (10500): VHDL syntax error at 3BM6Vorw.vhdl(32) near text "3"; expecting an identifier
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Der Code:
1 | LIBRARY IEEE;
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2 |
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3 | USE IEEE.std_logic_1164.ALL;
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4 |
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5 | ENTITY 3BM6Vor IS
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6 | PORT (clk: IN std_ulogic;
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7 | srst_n: IN std_ulogic;
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8 | a: IN std_ulogic_vector(0 DOWNTO 0);
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9 | q: OUT std_ulogic_vector(2 DOWNTO 0));
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10 | END 3BM6Vor;
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11 |
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12 | ARCHITECTURE behave OF 3BM6Vor IS
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13 |
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14 | TYPE state_type IS (1, 2, 3, 4, 5, 6);
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15 | SIGNAL next_state, current_state : state_type;
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16 |
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17 | -- comments for syf which comes with alliance : http://www-asim.lip6.fr/alliance
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18 | -- interpreted as comments by other tools
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19 | --pragma CURRENT_STATE current_state
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20 | --pragma NEXT_STATE next_state
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21 | --pragma CLOCK clk
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22 |
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23 | BEGIN
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24 | state_register: PROCESS (clk)
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25 | BEGIN
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26 | IF ( clk = '1' AND NOT clk'STABLE ) THEN
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27 | current_state <= next_state;
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28 | END IF;
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29 | END PROCESS;
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30 |
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31 | next_state_and_output_logic: PROCESS (current_state, a)
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32 | BEGIN
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33 | IF srst_n='0' THEN
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34 | next_state <= 1;
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35 | ELSE
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36 | CASE current_state IS
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37 | WHEN 1 => q <= "001";
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38 | IF a="0" THEN
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39 | next_state <= 2;
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40 | ELSIF a="1" THEN
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41 | next_state <= 1;
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42 | END IF;
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43 | WHEN 2 => q <= "010";
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44 | IF a="0" THEN
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45 | next_state <= 3;
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46 | ELSIF a="1" THEN
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47 | next_state <= 2;
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48 | END IF;
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49 | WHEN 3 => q <= "011";
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50 | IF a="0" THEN
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51 | next_state <= 4;
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52 | ELSIF a="1" THEN
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53 | next_state <= 3;
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54 | END IF;
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55 | WHEN 4 => q <= "100";
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56 | IF a="0" THEN
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57 | next_state <= 5;
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58 | ELSIF a="1" THEN
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59 | next_state <= 4;
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60 | END IF;
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61 | WHEN 5 => q <= "101";
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62 | IF a="0" THEN
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63 | next_state <= 6;
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64 | ELSIF a="1" THEN
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65 | next_state <= 5;
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66 | END IF;
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67 | WHEN 6 => q <= "110";
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68 | IF a="0" THEN
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69 | next_state <= 1;
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70 | ELSIF a="1" THEN
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71 | next_state <= 6;
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72 | END IF;
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73 | WHEN OTHERS => null;
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74 | END CASE;
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75 | END IF;
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76 | END PROCESS;
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77 |
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78 | END behave;
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Kann mich jemand über die Problematik aufklären? In QFSM lässt sich
alles ohne Probleme simulieren.
Grüsse,
Agrippa
