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void FLEXCAN1_init(void)
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{
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#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */
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uint32_t i=0;
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PCC->PCCn[PCC_FlexCAN1_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN1 */
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CAN1->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
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CAN1->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = SOSCDIV2 */
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CAN1->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT) */
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while (!((CAN1->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {}
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CAN1->CTRL1 = 0
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|CAN_CTRL1_PSEG2(3) /* Configure for 500 KHz bit time */
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|CAN_CTRL1_PSEG1(3) /* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */
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|CAN_CTRL1_PROPSEG(6) /* PRESDIV+1 = Fclksrc/Ftq=8 MHz/8 MHz*/
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|CAN_CTRL1_RJW(3) /* so PRESDIV = 0 */
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|CAN_CTRL1_SMP(1); /* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */
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/* PSEG1 = PSEG2 = 3 */
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/* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */
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/* RJW: since Phase_Seg2 >=4, RJW+1=4 so RJW=3. */
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/* SMP = 1: use 3 bits per CAN sample */
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/* CLKSRC=0 (unchanged): Fcanclk= Fosc= 8 MHz */
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for(i=0; i<64; i++ )
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{ /* CAN1: clear 16 msg bufs x 4 words/msg buf = 64 words */
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CAN1->RAMn[i] = 0; /* Clear msg buf word */
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}
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for(i=0; i<16; i++ )
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{ /* In FRZ mode, init CAN1 16 msg buf filters */
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//CAN1->RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */
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CAN1->RXIMR[i] = 0x00000000; /* Check No ID bits for incoming messages */
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}
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//CAN1->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */
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CAN1->RXMGMASK = 0x00000000; /* Global acceptance mask: check no ID bits */
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CAN1->RAMn[ 4*MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */
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/* EDL,BRS,ESI=0: */
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/* CODE=4: */
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/* IDE=0 */
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/* SRR, RTR, TIMESTAMP=0*/
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CAN1->RAMn[ 4*MSG_BUF_SIZE + 1] = 0x14440000;
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/* Msg Buf 4, word 1*/
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/* PRIO=0: CANFD not used */
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CAN1->MCR = 0x0000001F; /* Negate FlexCAN 1 halt state for 32 MBs */
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while ((CAN1->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {}
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/* Good practice: wait for FRZACK to clear (not in freeze mode) */
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while ((CAN1->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {}
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/* Good practice: wait for NOTRDY to clear (module ready) */
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}
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void FlexCAN1SendCanData(uint16_t id_u8, uint8_t* data_pu8, uint8_t lenght_u8)
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{
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uint32_t word0 = 0;
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uint32_t word1 = 0;
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uint32_t word2 = 0;
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uint32_t word3 = 0;
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word0 = 0x0C400000 | (8 << CAN_WMBn_CS_DLC_SHIFT); /* MB0 word 0 */
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/* bit 31: EDL=0*/
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/* bit 30: BRS=0*/
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/* bit 29: ESI=0*/
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/* bit 27-24: CODE=0xC*/
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/* bit 22: SRR=1 */
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/* bit 21: IDE=0 */
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/* bit 20: RTR=0*/
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/* bit 19-16: DLC=8*/
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/* bit 15-0: TIMESTAMP */
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word1 = ((uint32_t)id_u8 << 18); /* MB0 word 1 */
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/* Tx msg with STD ID */
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/* bit 31-29: PRIO = 0 */
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/* bit 28-18: ID (standard) */
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/* bit 17-0: ID (extended) */
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word2 = ((uint32_t)data_pu8[0] << 24)
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| ((uint32_t)data_pu8[1] << 16)
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| ((uint32_t)data_pu8[2] << 8)
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| ((uint32_t)data_pu8[3] << 0); /* MB0 word 2 */
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word3 = ((uint32_t)data_pu8[4] << 24)
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| ((uint32_t)data_pu8[5] << 16)
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| ((uint32_t)data_pu8[6] << 8)
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| ((uint32_t)data_pu8[7] << 0); /* MB0 word 3 */
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CAN1->IFLAG1 = 0x00000001; /* Clear CAN 1 MB 0 flag without clearing others*/
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CAN1->RAMn[ 0*MSG_BUF_SIZE + 1] = word1;
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CAN1->RAMn[ 0*MSG_BUF_SIZE + 2] = word2;
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CAN1->RAMn[ 0*MSG_BUF_SIZE + 3] = word3;
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CAN1->RAMn[ 0*MSG_BUF_SIZE + 0] = word0; // CODE is written here to activate transmission
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}
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