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Datei
prbs_checker.vhd
-- prbs_checker.vhd -- VHDL-93 synthesizable PRBS-16 checker with order and frame loss detection. -- Provides: sync flag, error counter (data integrity), loss counter (skipped frames). -- All outputs are marked with "keep" attribute. library
in „HW Link testen, auf datenintegrität, Frame loss“ · FPGA, VHDL & Co. ·
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Datei
sSimmics.txt
stiffstable.eps Real_ec.eps devices.tex mstee.eps stripline.eps Real_r.eps diac.eps mstee2.eps synthesis.tex TLpiece.eps differential.eps msvia.eps system.tex Unoise.eps diode.eps mszl.eps tcircuit.eps acanalysis.tex electromagnetics.tex nconnect.eps technical.tex acnoise.tex feuler.eps nconnect2.eps
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Datei
uSimmics.txt
stiffstable.eps Real_ec.eps devices.tex mstee.eps stripline.eps Real_r.eps diac.eps mstee2.eps synthesis.tex TLpiece.eps differential.eps msvia.eps system.tex Unoise.eps diode.eps mszl.eps tcircuit.eps acanalysis.tex electromagnetics.tex nconnect.eps technical.tex acnoise.tex feuler.eps nconnect2.eps
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Datei
technical.tex
lineardevices} \include{devices} \include{microstrip} \include{coplanar} \include{transline} \include{synthesis} \include{system} \include{electromagnetics} \include{maths} \begin{appendix} \chapter{Bibliography} % Release specific: Uncomment the following three lines. \def\chapter*{}% to suppress any header
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Datei
arctanFP.vhd
------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on entity arctanFP is port( nrst : in std_logic; clk : in std_logic; ceatan : in std_logic;-- startimpuls afkt Xinp :in std_logic_vector
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Datei
arctanFP.vhd
------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on entity arctanFP is port( nrst : in std_logic; clk : in std_logic; ceatan : in std_logic;-- startimpuls afkt Xinp :in std_logic_vector
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Datei
mulFP.vhd
simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY
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Datei
mulFP1.vhd
simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY mulFP1 IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid
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Datei
Configuration.h
curve to move acceleration, producing much smoother direction changes. * * See https://github.com/synthetos/TinyG/wiki/Jerk-Controlled-Motion-Explained */ //#define S_CURVE_ACCELERATION //=========================================================================== //============================= Z Probe
in „Custom 3D-Drucker zu ausgebuchtete Ecken“ · Mechanik, Gehäuse, Werkzeug ·
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PDF
RJPLB203TC1.pdf
Flame Class : UL 94V-0 DATE : 2008/02/04 R(REV:A4) MODEL NO. : RJPLB-203TC1 Manufacturer : SHIKONG SYNTHETIC FIBERS CORP. Grade : E202G30BK Flame Class : UL 94V-0 C. Shield Material : Cartridge t=0.25mm 10μ”-20μ” Thick Nickel over Brass D. LED Lamp (a) Lens Color: Transparent with color (b) Emitted Color
in „Suche Quelle für 10/100 Base-TX POE-Ethernet RJ45-Buchse mit Übertragern und Gleichrichtern“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Boot.txt
physically tagged, 2-way, linesize 32 bytes. Primary data cache 16kB, 4-way, linesize 32 bytes. Synthesized TLB refill handler (23 instructions). Synthesized TLB load handler fastpath (32 instructions). Synthesized TLB store handler fastpath (32 instructions). Synthesized TLB modify handler fastpath (
in „Pollin - Receiver-Mainboard mit Twin DVB-[T,C] Tuner, NXP PNX8950EH“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Boot_Kernel_Panic.txt
physically tagged, 2-way, linesize 32 bytes. Primary data cache 16kB, 4-way, linesize 32 bytes. Synthesized TLB refill handler (23 instructions). Synthesized TLB load handler fastpath (32 instructions). Synthesized TLB store handler fastpath (32 instructions). Synthesized TLB modify handler fastpath (
in „Pollin - Receiver-Mainboard mit Twin DVB-[T,C] Tuner, NXP PNX8950EH“ · Mikrocontroller und Digitale Elektronik ·
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Datei
main.c
test; init_platform(); //init the GPIOs XGpioPs Gpio; Gpio_init(&Gpio); //init the SPI XSpiPs Spi_synth; Spi_init(&Spi_synth); //init the Synthesizer Syn_init(&Spi_synth, SS, &Gpio, MUX); //set the frequency test = Syn_set_freq(94.5); //set the level Syn_setLevel(RF,dBm5); //switch on the RF output Syn_switch_output
in „ADF4351 kein Signal am N Divider Output“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Synthesizer.c
/* * Synthesizer.c * * Created on: 01.05.2015 * Author: Stephan */ #include "xgpiops.h" #include "xspips.h" #include "Synthesizer.h" #define FPFD 0.5 XSpiPs *Spi_InstancePtr; XGpioPs *GPIO_InstancePtr; uint8_t SlaveNr
in „ADF4351 kein Signal am N Divider Output“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Synthesizer.h
/* * synthesizer.h * * Created on: 01.05.2015 * Author: Stephan */ #ifndef SYNTHESIZER_H_ #define SYNTHESIZER_H_ //Register defines #define CBpos 0 //Register 0 #define FRACTIONALVALUEpos 3 #define INTEGERVALUEpos
in „ADF4351 kein Signal am N Divider Output“ · Mikrocontroller und Digitale Elektronik ·
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Datei
dic_reg_top_struct.vhd
active high read from data strobes ); end component; -- Optional embedded configurations -- pragma synthesis_off for all : register_array use entity dic_core.register_array; -- pragma synthesis_on begin -- Architecture concurrent statements -- HDL Embedded Text Block 1 eb1 ---slave bus attachment--- sbus_i.addr
in „Error: Identifier "unsigned" is not directly visible.“ · FPGA, VHDL & Co. ·
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Datei
IC_CC1101.cpp
halRfWriteReg(FREND0,0x10); //Front End TX Configuration halRfWriteReg(FSCAL3,0xEA); //Frequency Synthesizer Calibration halRfWriteReg(FSCAL2,0x2A); //Frequency Synthesizer Calibration halRfWriteReg(FSCAL1,0x00); //Frequency Synthesizer Calibration halRfWriteReg(FSCAL0,0x1F); //Frequency Synthesizer Calibration
in „In-Circuit radino CC1101 Modul Hängt im SPI Transfer“ · Mikrocontroller und Digitale Elektronik ·
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Datei
IC_CC1101.h
#define ADDR 0x09 // Address #define CHANNR 0x0A // Channel #define FSCTRL1 0x0B // Frequency synthesizer control 1 #define FSCTRL0 0x0C // Frequency synthesizer control 0 #define FREQ2 0x0D // Frequency control [23:16] #define FREQ1 0x0E // Frequency control [15:8] #define FREQ0 0x0F // Frequency control
in „In-Circuit radino CC1101 Modul Hängt im SPI Transfer“ · Mikrocontroller und Digitale Elektronik ·
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Datei
IntLib.txt
Analog Devices RF IF Detectors.IntLib AltiumLive\RF Wireless\Analog_Devices_RF_IF_Direct_Digital_Synthesis\Analog Devices RF IF Direct Digital Synthesis.IntLib AltiumLive\RF Wireless\Analog_Devices_RF_IF_Integrated_Transceivers_Transmitters_and_Receivers\Analog Devices RF IF Integrated Transceivers, Transmitters
in „Altium 5.1.x Offline Libs“ · Mikrocontroller und Digitale Elektronik ·
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Datei
RFM69.cpp
REG_FRFMID, freqHz >> 8); writeReg(REG_FRFLSB, freqHz); if (oldMode == RF69_MODE_RX) { setMode(RF69_MODE_SYNTH); } setMode(oldMode); } void RFM69::setMode(uint8_t newMode) { if (newMode == _mode) return; switch (newMode) { case RF69_MODE_TX: writeReg(REG_OPMODE, (readReg(REG_OPMODE) & 0xE3) | RF_OPMODE_TRANSMITTER
in „RFM69HW-Arduino Nano "Funkklingel"“ · HF, Funk und Felder ·
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Datei
RFM69.h
access #define RF69_MODE_SLEEP 0 // XTAL OFF #define RF69_MODE_STANDBY 1 // XTAL ON #define RF69_MODE_SYNTH 2 // PLL ON #define RF69_MODE_RX 3 // RX MODE #define RF69_MODE_TX 4 // TX MODE // available frequency bands #define RF69_315MHZ 31 // non trivial values to avoid misconfiguration #define RF69_433MHZ
in „RFM69HW-Arduino Nano "Funkklingel"“ · HF, Funk und Felder ·
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Datei
RFM69registers.h
0x20 #define RF_OPMODE_SLEEP 0x00 #define RF_OPMODE_STANDBY 0x04 // Default #define RF_OPMODE_SYNTHESIZER 0x08 #define RF_OPMODE_TRANSMITTER 0x0C #define RF_OPMODE_RECEIVER 0x10 // RegDataModul #define RF_DATAMODUL_DATAMODE_PACKET 0x00 // Default #define RF_DATAMODUL_DATAMODE_CONTINUOUS 0x40 #define
in „RFM69HW-Arduino Nano "Funkklingel"“ · HF, Funk und Felder ·
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Datei
IC_CC1101.h
#define ADDR 0x09 // Address #define CHANNR 0x0A // Channel #define FSCTRL1 0x0B // Frequency synthesizer control 1 #define FSCTRL0 0x0C // Frequency synthesizer control 0 #define FREQ2 0x0D // Frequency control [23:16] #define FREQ1 0x0E // Frequency control [15:8] #define FREQ0 0x0F // Frequency control
in „Homematic, Radino CSM“ · Mikrocontroller und Digitale Elektronik ·
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Datei
IC_CC1101.cpp
halRfWriteReg(FREND0,0x10); //Front End TX Configuration halRfWriteReg(FSCAL3,0xEA); //Frequency Synthesizer Calibration halRfWriteReg(FSCAL2,0x2A); //Frequency Synthesizer Calibration halRfWriteReg(FSCAL1,0x00); //Frequency Synthesizer Calibration halRfWriteReg(FSCAL0,0x1F); //Frequency Synthesizer Calibration
in „Homematic, Radino CSM“ · Mikrocontroller und Digitale Elektronik ·
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Datei
synthese.txt
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Sequenz Erkennung (01,11,10)- Moore Automat mit 3 - Prozessen entity R2R_FPGA is Port ( CLK, RESET, ENABLE : in bit; --Sekundäre Eingangssignale E : in bit_vector(1 downto 0); --Eingangsvektor A : out bit ); --Ausgangssignal end R2R_FPGA; architecture Behavioral of R2R_FPGA is type ZUSTAENDE is (Z0,Z1,Z2,Z3); --Aufzählungstyp signal ZUSTAND,FOLGE_Z:ZUSTAENDE; --Prozesskommunikation begin Z_SPEICHER: process (CLK,RESET) --Zustandsaktualisierung begin if RESET = '1' then ZUSTAND <= Z0 after
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Datei
div_16_16.vhd
however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. -- -- Reference: -- Command Line Tools User Guide, Chapter 23 -- Synthesis and Simulation Design Guide, Chapter 6 -- -----------------
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Datei
div_16_16.vhd
however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. -- -- Reference: -- Command Line Tools User Guide, Chapter 23 -- Synthesis and Simulation Design Guide, Chapter 6 -- -----------------
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Datei
OutputSynthesis.txt
ram_access @N: CG364 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":84:7:84:13|Synthesizing module fillRam @N: CG364 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main - Kopie.v":2:7:2:16|Synthesizing module ram_access @W: CS263 :"C:\Users\wagnersn\Desktop\VerilogRamTest\RamTest\main
in „If-Bedingung nach dem Einschalten, falsch initialisiert?“ · FPGA, VHDL & Co. ·
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Datei
Pible.syr.short.txt
inferred 41 D-type flip-flop(s). inferred 3 Adder/Subtractor(s). inferred 1 Xor(s). Unit <pibla> synthesized. Found 4-bit register for signal <digit>. Found 8-bit register for signal <segment>. Found 1-bit tristate buffer for signal <rs232_tx>. Found 8-bit register for signal <leds_8bit_GPIO_d_out>. Summary: inferred 20 D-type flip-flop(s). inferred 1 Tristate(s). Unit <sk_top> synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 4 16x8-bit dual-port RAM : 2 30x10-bit single-port RAM : 1 64x8-bit single-port
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Datei
rfm12.h
receiver #define EBB 6 //enable baseband #define ET 5 //enable transmitter #define ES 4 //enable synthesizer #define EX 3 //enable xtal(Quarz) #define EB 2 //enable brownout #define EW 1 //enable wakeup #define DC 0 //disable clock #define WKUP 12 //WakeUp: Der Aufweck-Timer ist abgelaufen extern uint16
in „Attiny13 spring t aus Hauptschleife“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SDR_SDRAM_Rev_1.10_2002-08.pdf
Column BA CS_N RAS_N CAS_N WE_N DQM DQ 1 2 ... n-4 n-3 n-2 n-1 n D.C. = Don't Care Simulation, Synthesis, Place-&-Route, & Results The SDR SDRAM Controller includes source files, a testbench, synthesis scripts, and support files for place-and- ® route using the Quartus II software version 2.1 targeting
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PDF
Strom-Messen.pdf
database, and a presentation they have drawbacks. The voltage drop across the shunt layer which synthesizes reports from this logged data. A key architectural separation is that applications are may e▯ect the AC device if the load has a high power draw. Also, the resistive heating results in thermal de
in „Auftrag zu vergeben“ · Markt ·
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Datei
daimond_synthesis_report.txt
Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.10.0.111.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995
in „Entscheidungshilfe MachXO2-7000HE/-XO3-6900C/-XO3LF-6900C“ · FPGA, VHDL & Co. ·
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Datei
RFM12BPCmd.h
define CMD_SET_POWER 0x8200 // [ er ] -> enables the whole receiver chain RF front end, baseband, synthesizer, crystal oscillator #define EN_RX 0x0080 // [ ebb ] -> the receiver baseband circuit can be separately switched on #define EN_BB_CIRCUIT 0x0040 // [ et ] -> switches on the PLL, the power amplifier, synthesizer, crystal oscillator // and starts the transmission (if TX register is enabled) #define EN_TX 0x0020 // [ es ] -> turns on the synthesizer #define EN_SYNTH 0x0010 // [ ex ] -> turns on the crystal
in „Rfm12B 686Mhz Bascom Testprogramm.“ · HF, Funk und Felder ·
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Datei
tft-lcd-controller-Overview-OpenCores.html
"></a> Progress </h2> <p id="p_Progress"> - Display one repeat line (800 pixels) stored in ROM synthesized in FPGA. <br> - Self-display word block (designed). <br> - (Have problem on hardware integration) Preparing display a frame stored in SSRAM which is on Logic Module. <br> - Parameter: <br> - VBP
in „Universal LCD+Input Modul mit MachXO2“ · FPGA, VHDL & Co. ·
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Datei
klingel.pl
%s %s", $tempo/2, $sound, $note; } elsif ($len == 3) { #2x 1/8 system sprintf "play -q -n synth %f %s %s", $tempo/2, $sound, $note; system sprintf "play -q -n synth %f %s %s", $tempo/2, $sound, $note; } elsif ($len == 4) { #3/8 system sprintf "play -q -n synth %f %s %s", $tempo*3/2, $sound, $note; } elsif ($len == 5) { #1/4 system sprintf "play -q -n synth %f %s %s", $tempo, $sound, $note; } elsif ($len == 6) { #2x 1/4 system sprintf "play -q -n synth %f %s %s", $tempo, $sound, $note; system sprintf "play -q -n synth %f %s %s", $tempo, $sound, $note;
in „DDR_UB880_Klingel“ · Offtopic ·
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Datei
Synth.asm
.nolist .include "tn2313def.inc" ; Define device ATtiny2313 .list ; ***Konstanten*** .equ F_CPU = 10000000 .equ F_ICR = 256 .equ PWM = F_CPU/F_ICR .equ BAUD = 31250 .equ BRC = (F_CPU/16/BAUD)-1 ; ***Defs*** .def rsreg = r15 .def rmp = r16 .def rbuf2 = r17 .def rudr = r18 .def rudr2 = r19 .def rudr3 = r20 .def rdaten = r21 .def rpkl = r22 .def rpkh = r23 .def rbuf = r24 .def rflag = r25 .def rZero = r0 .def rp1l = r3 .def rp1h = r4 .def rp2l = r5 .def rp2h = r6 .def rp3l = r7 .def rp3h = r8 .def rp4l = r9 .def rp4h = r10 ; ***SRAM*** .dseg .org SRAM_START .cseg .org 000000 ;Vectorinit rjmp Main
in „Attiny2313 Timer16 Bit, Normal Mode, unsauber“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Synth.asm
.nolist .include "tn2313def.inc" ; Define device ATtiny2313 .list ; ***Konstanten*** .equ F_CPU = 10000000 .equ F_ICR = 256 .equ PWM = F_CPU/F_ICR .equ BAUD = 31250 .equ BRC = (F_CPU/16/BAUD)-1 .equ MAXBUF = 40 ; ***Defs*** .def rsreg = r15 .def rmp = r16 .def rbuf2 = r17 .def rudr = r18 .def rudr2 = r19 .def rudr3 = r20 .def rdaten = r21 .def rpkl = r22 .def rpkh = r23 .def rbuf = r24 .def rflag = r25 .def rZero = r0 .def rbufmax = r1 .def rp1l = r3 .def rp1h = r4 .def rp2l = r5 .def rp2h = r6 .def rp3l = r7 .def rp3h = r8 .def rp4l = r9 .def rp4h = r10 ; ***SRAM*** .dseg .org SRAM_START .cseg
in „Attiny2313 Timer16 Bit, Normal Mode, unsauber“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Synth.asm
.nolist .include "tn2313def.inc" ; Define device ATtiny2313 .list .macro WriteSram ; (register, const) ldi XL, low(SRAM_START) ldi XH, high(SRAM_START) ldi rmp, 0 j0: cpi rmp, @1 breq j1 st X+, @0 inc rmp rjmp j0 j1: ldi XL, low(SRAM_START) ldi XH, high(SRAM_START) .endmacro .macro LongJump ; (rstate, const ,label) cpi @0, @1 brne j0 rjmp @2 j0: .endmacro .macro LoadMidiByteX ; (b0=2, b1=1),register movw YL, XL ;wenn negativ, dann in subrout rein sbiw YL, @0 cpi YL, SRAM_START brpl j1 rcall subrout j1: ;lade aus sramstelle ld @1, Y .endmacro .macro CompSetEQ ; (rcomp, const, rstate, stateconst)
in „Attiny2313 Timer16 Bit, Normal Mode, unsauber“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Synth.asm
.nolist .include "tn2313def.inc" ; Define device ATtiny2313 .list .macro WriteSram ; (register, const) ldi XL, low(SRAM_START) ldi XH, high(SRAM_START) ldi rmp, 0 j0: cpi rmp, @1 breq j1 st X+, @0 inc rmp rjmp j0 j1: ldi XL, low(SRAM_START) ldi XH, high(SRAM_START) .endmacro ; ***Konstanten*** .equ F_CPU = 10000000 ;.equ F_CPU = 26800000 .equ F_ICR = 256 .equ PWM = F_CPU/F_ICR .equ BAUD = 31250 .equ BRC = (F_CPU/16/BAUD)-1 .equ MAXBUF = 40 ; ***Defs*** .def rsreg = r15 .def rmp = r16 .def rmp2 = r17 .def rudr = r18 .def rkeyoff = r19 .def rstate = r20 .def rchannel = r21 .def rpkl = r22 .def rpkh
in „Attiny2313 Timer16 Bit, Normal Mode, unsauber“ · Mikrocontroller und Digitale Elektronik ·
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Datei
M6800_interface.v
11:0] col_end_addr; reg [10:0] row_start_addr; reg [10:0] row_end_addr; reg [12:0] start_addr/* synthesis syn_noprune=1 */; reg [3:0] end_addr; reg [11:0] col_addr; reg [10:0] row_addr; reg [20:0] page_start_addr/* synthesis syn_noprune=1 */; reg [7:0] vram_data; reg [15:0] ram_data; reg [7:0] r_control
in „Lattice Diamond - Fehlermeldung - State machine - Verilog - Brauche Hilfe“ · FPGA, VHDL & Co. ·
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Datei
Test_impl1_Report.htm
scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.</font> @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="E:\Program Files\diamond\3.12\synpbase\lib\lucent\xp.v:794:7:794:10:@N:CG364:@XP_MSG">xp.v(794)</a><!@TM:1628890923> | Synthesizing
in „Lattice Diamond - Fehlermeldung - State machine - Verilog - Brauche Hilfe“ · FPGA, VHDL & Co. ·
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Datei
xev.txt
NO VisibilityNotify event, serial 34, synthetic NO, window 0x1e00001, state VisibilityUnobscured Expose event, serial 34, synthetic NO, window 0x1e00001, (0,0), width 178, height 10, count 3 Expose event, serial 34, synthetic NO, window 0x1e00001, (0,10), width 10, height 58, count 2 Expose event, serial 34, synthetic NO, window 0x1e00001, (68,10), width 110, height 58, count 1 Expose event, serial 34, synthetic NO, window 0x1e00001, (0,68), width 178, height 110, count 0 FocusIn event, serial 34, synthetic NO
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Datei
rfm69registers.h
0x20 #define RF_OPMODE_SLEEP 0x00 #define RF_OPMODE_STANDBY 0x04 // Default #define RF_OPMODE_SYNTHESIZER 0x08 #define RF_OPMODE_TRANSMITTER 0x0C #define RF_OPMODE_RECEIVER 0x10 // RegDataModul #define RF_DATAMODUL_DATAMODE_PACKET 0x00 // Default #define RF_DATAMODUL_DATAMODE_CONTINUOUS 0x40 #define
in „PIC16f15244 RFM69 sendet nicht“ · Mikrocontroller und Digitale Elektronik ·
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Datei
MainActivity.java
/* synthetic */ boolean access$1500(MainActivity mainActivity) { return mainActivity.destroyed; } static /* synthetic */ void access$1600(MainActivity mainActivity) { mainActivity.process(); } static /* synthetic
in „Bluetooth LE BLE Daten von Powermeter entschlüsseln“ · Mikrocontroller und Digitale Elektronik ·
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Datei
gth_report_property.txt
IS_BD_CONTEXT bool true 0 IS_LOCKED bool true 0 KNOWN_TARGETS string* true instantiation_template synthesis simulation example changelog NAME string true gtwizard_ultrascale_0 PART string true xczu7ev-ffvc1156-2-e SELECTED_SIM_MODEL string false rtl STALE_TARGETS string* true instantiation_template SUPPORTED_TARGETS string* true instantiation_template synthesis simulation example changelog SUPPORTS_MODREF bool true 0 SW_VERSION string true 2020.1 UNSUPPORTED_SIMULATORS string* true USED_LICENSE_KEYS string* true USER_LOCKED bool false 0
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Datei
compile_Tasmota_stable_in_docker_container.txt
lib034/ESP8266Audio/libmad/stream.c.o Compiling .pio/build/tasmota32-DE/lib034/ESP8266Audio/libmad/synth.c.o Compiling .pio/build/tasmota32-DE/lib034/ESP8266Audio/libmad/timer.c.o Compiling .pio/build/tasmota32-DE/lib034/ESP8266Audio/libmad/version.c.o Compiling .pio/build/tasmota32-DE/lib034/ESP8266Audio
in „Dlock 11827 und Tasmota - compilieren für FW-Update“ · Haus & Smart Home ·
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Datei
compile_Tasmota_stable_in_docker_container_versuch3.txt
tasmota/lib034/ESP8266Audio/libmad/stream.c.o Compiling .pio/build/tasmota/lib034/ESP8266Audio/libmad/synth.c.o Compiling .pio/build/tasmota/lib034/ESP8266Audio/libmad/timer.c.o Compiling .pio/build/tasmota/lib034/ESP8266Audio/libmad/version.c.o Compiling .pio/build/tasmota/lib034/ESP8266Audio/libogg/bitwise.c.o
in „Dlock 11827 und Tasmota - compilieren für FW-Update“ · Haus & Smart Home ·
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Datei
RsdTestActivity.txt
(8); this.mSwtConfigDebug.setVisibility(4); } public /* synthetic */ void lambda$initView$1$RsdTestActivity(CompoundButton buttonView, boolean isChecked) { this.mAdapter.setIsShowDesc(isChecked); this.mAdapter.notifyDataSetChanged(); } public /* synthetic */ void
in „Wechselrichter Hoymiles HM-xxxx 2,4 GhZ Nordic Protokoll?“ · Mikrocontroller und Digitale Elektronik ·
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Datei
video.vhd
-- Copyright (c) 2015, $ME -- All rights reserved. -- -- Redistribution and use in source and synthezised forms, with or without modification, are permitted -- provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright notice, this list of conditions -- and the following disclaimer. -- -- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions -- and the following disclaimer in the documentation and/or other materials provided with the distribution. -- -- THIS SOFTWARE