Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    regf_decoder.vhd

    regf_decoder; architecture behaviour of regf_decoder is begin process(NUMBER) begin R_DECODE <= (others => '0'); case NUMBER is when "00000" => R_DECODE(0) <= '1'; when "00001" => R_DECODE(1) <= '1'; when "00010" => R_DECODE(2) <= '1'; when "00011" => R_DECODE(3) <= '1'; when "00100" => R_DECODE(4) <

    in „Registerspeicher“ · FPGA, VHDL & Co. ·

  • Datei

    sram_spi_code_vhdl.txt

    <= (others => '0'); sram_data <= (others => 'Z'); --sram_data als Eingang unsigned_ce_addr <= "1110"; unsigned_sram_data <= (others => '0'); sig_Reset <= not sig_Reset; end if; when "001" => -- LESEVORGANG if

    in „SRAM SPI Tristate Problem“ · FPGA, VHDL & Co. ·

  • Datei

    Code.txt

    counter2 + 1; --alle 240ms wird der counter1 zurückgesetzt if counter1 = 24000 then counter1 <=(others =>'0'); end if; end if; --Counter reset if int_reset = '1' then counter1 <= (others =>'0'); counter2 <= (others =>'0'); flag_empfang1 <= '0'; flag_empfang2 <= '0'; end if; int_reset <='0'; --wird ein

    in „Tri-State ausgänge (XC95144XL)“ · FPGA, VHDL & Co. ·

  • Datei

    uart_rx.vhd

    state_reg; s_next <= s_reg; n_next <= n_reg; b_next <= b_reg; rx_done_tick <='0'; case state_reg is when idle => if rx='0' then state_next <= start; s_next <= (others=>'0'); end if; when start => if (s_tick = '1') then if s_reg=7 then state_next <= data; s_next <= (others=>'0'); n_next <= (others=>'0'); else s_next <= s_reg + 1; end if; end if; when data => if (s_tick = '1') then if s_reg=15 then s_next <= (others=>'0'); b_next <= rx & b_reg(7 downto 1) ; if n_reg=(DBIT-1) then state_next <= stop ; else n_next <= n_reg + 1; end if; else s_next

    in „UART Test Hilfe!“ · FPGA, VHDL & Co. ·

  • Thread

    Einfaches Register mit AXI Interface

    S_AXI_WREADY <= '0'; S_AXI_AWREADY <= '0'; state <= addr_wait; address <= (others=>'0'); write_enable <= '0'; else case state is when addr_wait => -- wait for a read or write address and latch it in if S_AXI_ARVALID =

    std_logic_vector(3 downto 0) := (others => '0'); signal S_AXI_BREADY : std_logic := '0'; signal S_AXI_ARADDR : std_logic_vector(31 downto 0) := (others => '0'); signal S_AXI_ARVALID : std_logic := '0'; signal S_AXI_RREADY

    FPGA, VHDL & Co. ·Student · ·6 Antworten

  • Thread

    AX8 - PINB - Multi-source-Error (Spartan 3E/VHDL)

    when others => --ignorieren end case; tmp_adr <= x"00"; else tmp_adr <= MyPortA; end if; end

    so wird Kombinatorik erzeugt if MyPortA = x"00" then case tmp_adr is when x"00" => -- belegt ;-) when x"01" => LED <= MyPortC; when x"02" => MyPortB <= "0000000" & SW(0); when others => --ignorieren

    FPGA, VHDL & Co. ·Andreas Weschenfelder · ·4 Antworten

  • Datei

    arctanFP.vhd

    3:= 0; BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN stateatan <= 0; ce1 <= '0'; --InpA <= (OTHERS => '0'); ---InpB <= (OTHERS => '0'); cntrclk := 0; --(OTHERS => '0'); ELSE CASE stateatan IS WHEN 0 => IF ceatan = '1' THEN stateatan <= 1; --InpA <= Xinp; --InpB <= Yinp; cntrclk := 1;-- time for

    in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. ·

  • Thread

    Xilinxs Fehlermeldung CPLD

    port_value <= Eingang2; end if; //Multiplexer end if; end process; PORTXXX <= port_value when (port_oe = '1') else (others => 'Z'); //Buffer [/code] Ich habe mir wirklich keine Gedanken darüber gemacht, wie das letztendlich in Hardware aussieht. Auf jeden fall noch mal Danke, ich habe

    port_value <= Eingang2; end if; end process; -- Port hochohmig bei Fehler PORTXXX <= port_value when (error1 = '0' and error2 = '0') else (others => 'Z'); // Buffer [/vhdl] > Zum asynchronen Reset. Ich habe mich hier an einem Code Template von > Xilinxs orientiert. Und auch die meisten Bücher

    FPGA, VHDL & Co. ·batch · ·7 Antworten

  • Thread

    Datenaustausch Entity und NIOS II

    as_write = '1' then -- Schreiben von Registern case as_address is when x"00" => bla lba when others => null; end case; end if; end if; end behave in NIOS hast Du dann IOWR_32DIRECT(BASE, adresse, value) und IORD_32DIRECT(BASE, adresse

    Ja, x"00" ist die interne Registeradresse case as_address is when x"00" => mein_register0 <= as_writedata; when x"01" => mein_register1 <= as_writedata; ... when others => null; end case; Danach erstellst Du einfach eine Komponente

    FPGA, VHDL & Co. ·Sebi · ·4 Antworten

  • Thread

    Probleme mit Statemachine

    => cyc_o <= '1'; stb_o <= '1'; we_o <= '1'; when S_FINITE => done <= '1'; when others => null; end case; end process; process (state,cmd,ack_i) begin next_state <= state; case state is when

    end if; when S_FINITE => next_state <= S_IDLE; when others => next_state <= S_FINITE; end case; end process; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Chris · ·13 Antworten

  • Thread

    Braucht ein CPLD einen schnellen Takt?

    when 5 => leds <= "0000100000"; when 4 => leds <= "0000010000"; when 3 => leds <= "0000001000"; when 2 => leds <= "0000000100"; when 1 => leds <= "0000000010"; when 0 => leds <= "0000000001"; when others=>leds <= "0101010101"; end case; end process; end Behavioral; [/vhdl] Nun habe ich wieder 2 Fragen: 1. -- Signal konvertieren

    FPGA, VHDL & Co. ·Thomas Gie · ·45 Antworten

  • Thread

    "expecting End" - Fehler in Modelsim

    ' after 20 ns; when others => A <= '00' after 20 ns; end case; end process AUS_SN; end SEQUENZ; [/vhdl] Und hier die Fehlermeldung: vcom -work work -2002 -explicit -stats=none C:/Modeltech_pe_edu_10.4/examples

    Anführungszeichen (") ausgedrückt. Vgl. Zeile 79, 80 - Im Kombinatorischen Schaltnetz "UE_SN" fehlt ein "when others" Viele Grüße

    FPGA, VHDL & Co. ·David Höhle · ·2 Antworten

  • Datei

    uart_tx.vhd

    s_reg; n_next <= n_reg; b_next <= b_reg; tx_next <= tx_reg ; tx_done_tick <= '0'; case state_reg is when idle => tx_next <= '1'; if tx_start='1' then state_next <= start; s_next <= (others=>'0'); b_next <= din; end if; when start => tx_next <= '0'; if (s_tick = '1') then if s_reg=15 then state_next <= data; s_next <= (others=>'0'); n_next <= (others=>'0'); else s_next <= s_reg + 1; end if; end if; when data => tx_next <= b_reg(0); if (s_tick = '1') then if s_reg=15 then s_next <= (others=>'0'); b_next <= '0' & b_reg(7

    in „UART Test Hilfe!“ · FPGA, VHDL & Co. ·

  • Datei

    counter.vhd

    std_logic_vector(31 downto 0); begin process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); count <= (others => '0'); else if count = x"FFFFFFFF" then count <= (others => '0'); else count <= count +1; end if; case switches is when "0001" => q <= count(7 downto 0); when "0010" => q <= count(15 downto 8); when "0100" => q <= count(23 downto 16); when "1000" => q <= count(31 downto 24); when others => q <= (others => '0'); end case; end if; end if; end process; end Behavioral;

    in „LED-Zähler mit Xilinx CPLD“ · FPGA, VHDL & Co. ·

  • Thread

    Datenabtastung und Case-Problem

    [vhdl] process(CLK,datain,clockin) -- CLK: CPLD-Clock zum Abtasten: begin case switch is when "00" => --BUFFER dataout <= datain; clockout <= clockin; when "01" => --SCRAMBLER if(rising_edge(CLK)) then ... when others => --DESCRAMBLER if(rising_edge(CLK))

    process(datain, clockin, switch) -- CLK: CPLD-Clock zum Abtasten: begin case switch is when "00" => --BUFFER dataout <= datain; clockout <= clockin; when "01" => --SCRAMBLER dataout <= scramberl_out; clockout <= clockin; when others => --DESCRAMBLER

    FPGA, VHDL & Co. ·Geo · ·8 Antworten

  • Datei

    counter.vhd

    std_logic_vector(31 downto 0); begin process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); count <= (others => '0'); else if enable = '0' then -- if count = x"FFFFFFFF" then --Counter anuell resetten... -- count <= (others => '0'); --else count <= count +1; --end if; end if; case switches is when "0001" => q <= count(7 downto 0); when "0010" => q <= count(15 downto 8); when "0100" => q <= count(23 downto 16); when "1000" => q <= count(31 downto 24); when others => q <= (others => 'Z'); --Schaltet

    in „LED-Zähler mit Xilinx CPLD“ · FPGA, VHDL & Co. ·

  • Datei

    Display.vhd

    ", -- 8 "0010000" when "1001", -- 9 "0001000" when "1010", -- A "0000011" when "1011", -- B "1000110" when "1100", -- C "0100001" when "1101", -- D "0000110" when "1110", -- E "0001110" when "1111", -- F "1000000" when others

    in „Binär zu BCD wandlung“ · FPGA, VHDL & Co. ·

  • Thread

    Wo ist hier zb die sogenannte Verdrahtung im VHD-Programm?

    terminal_count <= '1'; count <= (others => '0'); else terminal_count <= '0'; end if; end process; process begin wait until rising_edge(clk); if terminal_count = '1' then case state is when "01" => state <= "10"; when "10" => state <= "01"; when others => state <= "01"; end case

    FPGA, VHDL & Co. ·Peter B. · ·2 Antworten

  • Thread

    I2C Master bekommt kein ACK

    else FPGA_I2C_SDAT<=data_out(data_index); fsm_spi<=ack3; end if; when ack3=> LEDR(9 downto 6)<="1001"; FPGA_I2C_SDAT<='Z'; if(FPGA_I2C_SDAT='0')then fsm_spi<= stop; end if; when sby => LEDR(9 downto 6)<="0001

    FPGA_I2C_SDAT<='1'; fsm_spi<=sby; spi_clk_en<='0'; when others=>NULL; end case; end if; end process; process(clk_SPI) begin if rising_edge(clk_SPI) and single_shot='1' then single_shot<='0'; if (KEY(0)='0' ) then ----wake up

    FPGA, VHDL & Co. ·GS · ·7 Antworten

  • Thread

    Vivado Warnung, "Sequential element unused" warum tritt sie auf?

    led_out(7) <= not disp_data(38); count_disp := 0; when others => an_out <= "11111111"; end case; end if; end if; end process; G1_Bcd_Dec: Bcd_Dec port map (hex,bcd); end Behavioral; [/vhdl] Er benutzt

    <= "00100001"; --D --> "01011110" when "1110" => bcd <= "00000110"; --E --> "01111001" when "1111" => bcd <= "00001110"; --F --> "01110001" when others => bcd <= "00000000"; end case; end process; end Behavioral;

    FPGA, VHDL & Co. ·Matze · ·13 Antworten

  • Datei

    user_logic.vhd

    , slv_reg1 ) is begin case slv_reg_read_sel is when "10" => slv_ip2bus_data <= slv_reg0; when "01" => slv_ip2bus_data <= slv_reg1_1 or slv_reg1_2;--slv_reg1; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC

    in „Custom IP-Core für Mittelwert/Standardabweichung“ · FPGA, VHDL & Co. ·

  • Thread

    Unerklärlicher Type error mit std_logic_vector

    --Selektor mit der der korrekte Wert für die LevelRegister übernommen wird 1 when (iRisingKeyEdge(0) = '1'), 2 when (iRisingKeyEdge(1) = '1'), 0 when others; SelektorLevelB : with iRisingKeyEdge select oSelLevelB <= 1 when (iRisingKeyEdge(2) = '1'), 2 when (iRisingKeyEdge(3) = '1'), 0 when others; end architecture Beh; [/vhdl] ist die Syntax vom with Select falsch oder darf man beim with kein array benutzen? Für Hilfe wäre ich sehr dankbar!

    FPGA, VHDL & Co. ·rhood · ·2 Antworten

  • Datei

    generator.txt

    0; when 61 => return 0; when 62 => return 0; when 63 => return 0; when others => return 0; end case; end function sinus; begin function_generator: process(clk10) variable prescaler: std_logic_vector(7 downto

    in „VHDL-Typenkonvertierung“ · FPGA, VHDL & Co. ·

  • Datei

    DISPLAY.vhd

    std_logic); end Broke; architecture verhalten of Broke is begin with cardsum select broke <= '1' when "10110", '1' when "10111", '1' when "11000", '1' when "11001", '1' when "11010", '1' when "11011", '1' when "11100", '1' when "11101", '1' when "11110", '1' when "11111", '0'when others; end verhalten

    in „Rechnen mit signed und unsigned“ · FPGA, VHDL & Co. ·

  • Datei

    Neuron_tb.vhd

    downto 0) := (others => '0'); signal Mem_Data_In : std_logic_vector(15 downto 0) := (others => '0'); signal Input : std_logic_vector(15 downto 0) := (others => '0'); signal Address : std_logic_vector(6 downto 0) := (others

    in „Pipeline MAC-Unit: Problem mit Latency“ · FPGA, VHDL & Co. ·

  • PDF

    lab10.pdf

    <= S0; case (state) is when S0 => if (x = '1') then next_state <= S1; end if; when S1 => if (x = '0') then next_state <= S1; end if; when others => next_state <= S0; end case; end process; The state assignments can be of one-hot

    in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. ·

  • Datei

    Quicksort.vhd

    increment : process (clock_quicksort) begin if falling_edge (clock_quicksort) then case state is when idle_state => read_address_quicksort_internal <= (others => '0'); write_address_quicksort_internal <= (others => '0'); state <= data_in_state; when data_in_state => write_address_quicksort_internal

    in „hinder the constant cleaning in the block“ · FPGA, VHDL & Co. ·

  • Thread

    integer und case

    case Konstrukt habe ich. Wenn ich in einem Prozess einen Mux bauen will, geht das ja u.A. mit case...when. Benutze ich als Auswahlkriterium einen unsigned Vektor funktioniert es. Ich habe nun probiert einen integer zu benutzen und dabei bin ich gescheitert. Wenn ich den integer durch unsigned(int, breite

    end probe; architecture Behavioral of probe is (...) signal s_sel: unsigned(1 downto 0) := (others=>'0'); (...) mux: process begin (..) case s_sel is when "00" => when others => end case; s_sel <= s_sel + 1; if( to_integer(s_sel) >= STELLEN) then s_sel <= (others

    FPGA, VHDL & Co. ·der Steff · ·2 Antworten

  • Thread

    Vergleichsalgorithmus gibt seltsames Ergebnis aus

    signal eing_z3 : std_logic_vector (11 downto 0); ... if res = '1' then eing_z1 <= (others => '0'); eing_z2 <= (others => '0'); eing_z3 <= (others => '0'); elsif clk'event and clk = '1' then eing_z1 <= eing; eing_z2 <= eing_z1; eing_z3 <= eing_z2; .

    die Gefahr geringer, dass Du Dir irgendwo Latche einfängst. Also z. B. TARGET <= VALUE_1 when CONDITION_1 else VALUE_2 when CONDITION_2 else . . . VALUE_n; Gruss Axel PS: Allerdings habe ich noch nicht verstanden, was Du eigentlich

    FPGA, VHDL & Co. ·Black Friday · ·11 Antworten

  • Datei

    sieben_segment.vhd

    segm<="1100000"; -- b -- WHEN "1100"=>segm<="0110001"; -- C -- WHEN "1101"=>segm<="1000010"; -- d -- WHEN "1110"=>segm<="0010000"; -- E -- WHEN "1111"=>segm<="0111000"; -- F -- WHEN OTHERS=>segm<="0000000"; -- mögliche andere Fälle

    in „Fehler im VHDL-Quellcode“ · FPGA, VHDL & Co. ·

  • Thread

    MII Synchronisierung, Ethernet

    process(rst, clk) begin if rst = '1' then rxstate <= idle; rx_buffer <= (others => '0'); elsif rising_edge(clk) and (rxclk_sync = '0') then rx_stb_o <= '0'; frame_start <= '0'; case rxstate is when idle => if rxdv = '1' then rxstate <= wa; rx_buffer <= (others => '0'); end if; when wa => rxstate <= data_lo; when data_lo => frame_start <= '1'; if rxdv = '0' then rxstate

    FPGA, VHDL & Co. ·Tobias P. · ·9 Antworten

  • Thread

    SDRAM Timing. Geht das so? READ NOP NOP READ?

    cmd_ready = '1' and stp_refresh = '1' and clkenable = '1' ) then case state is when ST_INIT => --..... when ST_WRITE => --..... when ST_READ => cmd_wr <= '0'; cmd_address <= addr_cnt; --x"0000A0"

    else addr_cnt <= addr_cnt + '1'; end if; when others => null; end case; else cmd_enable <= '0'; end if; end if; end process test; [/vhdl] Dieses Bild zeigt nun das Timing direkt am IC gemessen mittels

    FPGA, VHDL & Co. ·Holger K. · ·9 Antworten

  • Datei

    IO_mux.vhd

    signal adr_int : integer; begin adr_int <= conv_integer(adr_bus); -- IO read mux data_bus <= read_bus when rd = '0' and cs = '0' else (others=>'Z'); -- register write access process(wr) begin if rising_edge(wr) then if cs='0' then my_reg(adr_int) <= data_bus; end if; end if; end process; -- register read

    in „VHDL: Multiplexer mit generischer Anzahl zu muxender Busse?“ · FPGA, VHDL & Co. ·

  • Thread

    SPI Master 1. Übertragung wird verschluckt

    when 3 => TX_Start <= '1'; state <= 4; when 4 => if TX_Done = '1' then TX_Start <= '0'; state <= 5;

    when 6 => TX_Data <= x"8" & ValueB & x"0"; -- 2. Byte mit ValueB state <= 7; when 7 => if delay_counter > 0 then

    FPGA, VHDL & Co. ·Benjamin · ·5 Antworten

  • Datei

    data_to_bram.vhd

    downto 0) <= rx_data_in; when 3 => k2_i(15 downto 8) <= rx_data_in; when 4 => p1_i(7 downto 0) <= rx_data_in; when 5 => p1_i(15 downto 8) <= rx_data_in; when 6 => p2_i(7 downto 0) <= rx_data_in; when 7 => p2_i(15 downto 8) <= rx_data_in; when 8 => fx_i(7 downto 0) <= rx_data_in; when 9 => fx_i(15 downto 8) <= rx_data_in; when 10 => fy_i(7 downto 0) <= rx_data_in; when 11 => fy_i(15 downto 8) <= rx_data_in; when 12 => cx_i(7 downto 0) <=

    in „Ethernet Problem“ · FPGA, VHDL & Co. ·

  • Datei

    calc.vhd

    downto 0); variable e2: std_logic_vector(39 downto 0); begin next_state <= state; case (state) is when st0_idle => next_state <= st0_idle; when st1_calc1 => mu1_a <= num1; mu1_b <= num2; next_state <= st2_calc2; when st2_calc2 => result12 <= mu1_product; next_state <= st3_calc3; when st3_calc3 => mu1_a <= num3; mu1_b <= num4; next_state <= st4_calc4; when st4_calc4 => result34 <= mu1_product; next_state <= st5_calc5; when st5_calc5 => result <= result12 + result34; next_state <= st6_idle; when st6_idle => next_state <= st6_idle; when others => next_state

    in „Latch bei Berechnung mittels FSM“ · FPGA, VHDL & Co. ·

  • Datei

    IO_mux.vhd

    integer range 0 to 15; begin adr_int <= conv_integer(adr_bus); -- IO read mux data_bus <= read_bus when rd = '0' and cs = '0' else (others=>'Z'); -- register write access process(wr) begin if rising_edge(wr) then if cs='0' then my_reg(adr_int) <= data_bus; end if; end if; end process; -- register read

    in „VHDL: Multiplexer mit generischer Anzahl zu muxender Busse?“ · FPGA, VHDL & Co. ·

  • Thread

    Shiften in VHDL.

    [vhdl] case (CounterX) is when "000" => out <= "00000001"; when "001" => out <= "00000010"; when "010" => out <= "00000100"; when "011" => out <= "00001000"; when "100" => out <= "00010000"; when "101" => out <= "00100000"; when "110" => out <= "01000000"; when "111" => out <= "10000000"; when others => out <= "00000000"; end case

    FPGA, VHDL & Co. ·peter · ·13 Antworten

  • Thread

    VHDL UART mehrere Vectoren empfangen und einordnen

    end process; RX_Data <= rxsr; --RX_DATA müsste in den Vektor eingeordnet werden. RX_Busy <= '1' when (rxbitcnt<9) else '0';

    Datenarray TYPE RX_Type is array (0 to 15) of STD_LOGIC_VECTOR(7 downto 0); Signal RX_Data : RX_Type (others => (others => '0'); und dann mit ner schleife halt das Array durchgehen, bis du alle Bytes empfangen hast. So in etwa würde ich das zumindest machen ;D

    FPGA, VHDL & Co. ·Neuling · ·17 Antworten

  • PDF

    P20101.pdf

    VCC_C becomes lower than VDD whenever VDD, VDDIO is ON and VCC_C is OFF. VCC_C should be disabled when it is OFF. - 15 - REV.: X02 2008/03/20 This document contains confidential and proprietary inNeither it nor the information contained herein shall be disclosed to others or duplicated or used for others

    in „RiTdisplay - Ansteuerung“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    HMCAD1511.vhd

    :=(others => '0'); signal Byte_Serdes_4: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_5: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_6: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_7: std_logic_vector(7 downto 0):=(others => '0'); signal Byte_Serdes_FCLK: std_logic_vector(7 downto 0):=(others => '0'); signal TwoByte_Serdes_0: std_logic_vector(15 downto

    in „HMCAD1511 Interface“ · FPGA, VHDL & Co. ·

  • PDF

    AA51880.pdf

    ELECTRICAL CHARACTERISTICS Ta=25℃, Vcc=4.8V LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT MIN TYP MAX When output is OFF - 5 8 mA ICC Operating current When output is ON - 25 28 mA VOL Output voltage "L" Load resistor 20Ω - 0.1 0.2 V VOH Output voltage "H" Load resistor 240Ω 3.5 - - V External PNP transistor

    in „Servo-Elektronik mit AA51880 Controller zerstört sich selbst“ · Analoge Elektronik und Schaltungstechnik ·

  • PDF

    AA51880.pdf

    ELECTRICAL CHARACTERISTICS Ta=25℃, Vcc=4.8V LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT MIN TYP MAX When output is OFF - 5 8 mA ICC Operating current When output is ON - 25 28 mA VOL Output voltage "L" Load resistor 20Ω - 0.1 0.2 V VOH Output voltage "H" Load resistor 240Ω 3.5 - - V External PNP transistor

    in „Servo-Elektronik mit AA51880 Controller zerstört sich selbst“ · Analoge Elektronik und Schaltungstechnik ·

  • Thread

    Zählermit Einstellmöglichkeiten

    reset) begin --if reset = '1' then -- count_q <= (others => '0'); --elsif rising_edge(clk) then if rising_edge(clk) then if clr = '1' then count_q <= (others => '0'); elsif cnt_ena = '1' then count_q <= count;

    counting : PROCESS (reset, clock) BEGIN IF(reset ='1') THEN count <= (others => '0'); cmp <= (others => '0'); tmp <= (others => '0'); tmp_pre<=(others => '0'); twostp<= (others => '0'); ELSIF(rising_edge

    FPGA, VHDL & Co. ·Jonas K. · ·24 Antworten

  • Datei

    fbas_enc.vhd

    " => vout <= "00110"; when "011" => vout <= "01000"; when "100" => vout <= "01011"; when "101" => vout <= "01101"; when "110" => vout <= "01011"; when "111" => vout <= "01000"; when others => vout <= "01000"; end case; else case

    in „Video-Farbausgabe mit ATmega88“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    interface.vhd

    RST) begin if RST = '0' then cnt <= 0; elsif CLK_PLL = '1' and CLK_PLL'event then case state is --when GAIN_SWITCH => cnt <= 0; when CONFIG_1 => cnt <= 0; when CONFIG_2 => cnt <= 0; when CONFIG_3 => cnt <= 0; when CH_SEL => cnt <= 0; when START => if cnt < 4 then cnt <= cnt + 1; elsif cnt >= 4 and rts_master_ar_s

    in „Sehr seltsames Verhalten eines VHDL-Designs, Bitte um Hilfe“ · FPGA, VHDL & Co. ·

  • Thread

    eigene Daten/Steuerregister erstellen

    if (wr_n= '0') then case address is when x"00" => Reg_0x00 <= write_data; when x"01" => Reg_0x01 <= write_data; when x"02" => Reg_0x02 <= write_data; end case; end if; so oder so ähnlich

    process(RegisterFile, reg_idx_i) is begin if (reg_idx_i = -1) then reg_o <= (others => 'X'); else reg_o <= RegisterFile(reg_idx_i); end if; end process RegisterFileRead; RegisterFileWrite : process (clk_i, res_i) is begin --Reset

    FPGA, VHDL & Co. ·noname · ·11 Antworten

  • Thread

    SPLD (GAL) - welche Software

    when "10" => digit <= s10; an <= "1011"; dp <= '1'; when others => digit <= m; an <= "0111"; dp <= '0';

    digit=1 else "0100100" when digit=2 else "0110000" when digit=3 else "0011001" when digit=4 else "0010010" when digit=5 else "0000010" when digit=6 else

    FPGA, VHDL & Co. ·Adrian Wallaschek · ·63 Antworten

  • Thread

    Alternative Zählerbeschreibung

    ena <= '1'; else ena <= '0'; end if; end if; end process; sig <= cnt(12) when rising_edge(clk); end architecture; [/vhdl]

    ena : std_logic := '0'; begin process(reset, clk) begin if reset = '1' then cnt <= (others => '0'); cnt2 <= (others => '0'); ena <= '1'; elsif rising_edge(clk) then if (ena = '1') then -- Splittung der Kombinatorik cnt <= cnt + 1; end if;

    FPGA, VHDL & Co. ·Harry · ·35 Antworten

  • Thread

    Division mit verschiedenen Werten

    zahl1,zahl2,zahl3,i) variable tmp : integer range -256 to 255; begin case i is when 1 => tmp := (zahl1 + zahl2); when 2 => tmp := (zahl1 + zahl3); when others => tmp := (zahl2 + zahl3); -- Defaultzuweisung end case; result <= tmp/2; end process

    combinational path delay: 16.236ns process (zahl1,zahl2,zahl3,i) begin case i is when 1 => result <= ((zahl1 + zahl2) / 2); when 2 => result <= ((zahl1 + zahl3) / 2); when others => result <= ((zahl2 + zahl3) / 2); -- Defaultzuweisung end case; end

    FPGA, VHDL & Co. ·Gast · ·18 Antworten