Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    sram.vhd

    then state<="000"; ramwe <= '1'; ram_io <= "ZZZZZZZZ"; elsif rising_edge(clk) then case state is when "000" => --ram_io<= (others => 'Z'); if we='1' then state<="001"; else state<="100"; end if; -- do<=ram_io; when "001" => ram_io<=di; ramwe <= '1'; ram_oe <= '1'; state <= "010"; when "010" => ramwe <='0'; ram_io<=di; state <="000"; when "100" => ramwe <= '1'; ram_oe <='0'; ram_io<= (others => 'Z'); state<="101"; when "101" => do<=ram_io; state <= "000"; when others => state <= "000"; end case; end if; end process; end Behavioral;

    in „Externens Ram statt FPGA RAM“ · FPGA, VHDL & Co. ·

  • Thread

    Wittig(welec) DSO W20xxA Open Source Firmware (Teil4) Gesperrt

    I noticed when some values are below certain >> levels then zero is showed: >Hmmm, difficult. I think it is because of the interpolation. I will >check if it can be improved. You knew the job was difficult when

    @Luc & all others >> When QM is on, changing Time Base sometimes get corruption on the screen >Yes I noticed this too and I'm searching for the reason. I hope I can >fix it soon. Unfortunately I wasn't able

    Mikrocontroller und Digitale Elektronik ·Kurt B. · ·1093 Antworten

  • Datei

    bit.vhd

    "1000"=>LED<="1001"; when"1001"=>LED<="1010"; when"1010"=>LED<="1011"; when"1011"=>LED<="1100"; when"1100"=>LED<="1101"; when"1101"=>LED<="1110"; when"1110"=>LED<="1111"; when"1111"=>LED<="0000"; when others=>null; end case;

    in „4 Bit Zähler“ · FPGA, VHDL & Co. ·

  • Datei

    tasten.vhd.txt

    ", '1' when "0010000000", '1' when "0100000000", '1' when "1000000000", '0' when others; with EINSTELL select EINSTINT <= '0' when "0000", '1' when "0001", '1' when "0010", '1' when "0100", '1' when "1000", '0' when others; INTERRUPT <= TASTINT or EINSTINT; end VERHALTEN;

    in „VHDL - Problem“ · FPGA, VHDL & Co. ·

  • Datei

    spi2in.vhd

    bitcounter = Laenge --> alle Bits uebertragen signal rx_reg_c : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); --Cosinus Register signal rx_reg_s : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); --Sinus Register signal rx_reg_temp_c : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); --Cosinus

    in „FSM mit ADC synchronisieren“ · FPGA, VHDL & Co. ·

  • Thread

    Kann ein Automat "abstürzen" ?

    weggelassen) process (Takt) begin if Takt = '1' and Takt'event then case zustand is when a => blabla leds <= "001"; if irgendwas then zustand <= b; end if; when b => blabla leds <= "010"; if irgendwas then

    Anweisung reinpacken - dann hast du auf jeden Fall alle möglichen Zustände abgedeckt: case bla is when a => when b => when c => when others => end case; Gruß, Thomas

    FPGA, VHDL & Co. ·Hans · ·12 Antworten

  • Thread

    Universeller VGA Controller

    vertical_counter vertical_counter <= vertical_counter + 1; horizontal_counter <= (others => '0'); end if; -- Vertical Sync Sync Pulse Time = 521 Lines if (vertical_counter = vga_mode.vertical_sync_pulse_time) then vertical_counter <= (others => '0'

    process (clock) is begin if rising_edge(clock) then case vgamodus is when vga480x640at60 => vga_mode <= vgamode480x640at60; when vga600x800at72 => vga_mode <= vgamode600x800at72; end case; end if; end process; end architecture rtl; [/vhdl]

    FPGA, VHDL & Co. ·Hans-Werner · ·8 Antworten

  • PDF

    RGS15128128WR000.pdf

    contains confidential and propNeither it nor the information containedherein shall be disclosed to others or duplicated or used for others without the express written consent of RiTdisplay. http://www.ritdisplay.com REVISION RECORD REV. REVISION DESCRIPTION REV. DATE REMARK X01 ■ INITIAL RELEASE 2008.

    in „OLED Display mit SSD1327 Controller ansteuern“ · Mikrocontroller und Digitale Elektronik ·

  • Thread

    Sinus Phasen Verschiebung

    architecture Behavioral of Blinky_test is --signal counter : std_logic_vector(9 downto 0) := (others => '0'); signal clk : std_logic := '0'; signal clk_div2 : std_logic := '0'; signal position_sinus1 : integer range 0 to 249 := 0; signal triangle : std_logic_vector(11 downto 0) := (others => '

    - to be testet with 10MHz or 10kHz; one sample needs falling and (!) rising edge --LED0 <= '1' when counter < "0111111111" else '0'; LED0 <= '1' when position_sinus1 < 125 else '0'; --LED1 <= clk_div2;--KEY1 and COMP_IN; Inst_key_debounce: key_debounce PORT MAP( clk => clk, reset

    FPGA, VHDL & Co. ·otti · ·8 Antworten

  • Datei

    debounce_mit_tb.vhd

    RTL of debounce is -- registers signal state0, state1, state2: std_logic_vector(7 downto 0) := (others => '0'); signal key_pressed_old: std_logic_vector(7 downto 0) := (others => '0'); signal key_pressed: std_logic_vector(7 downto 0) := (others => '0'); begin process(clk) begin if rising_edge(clk) then

    in „Suche Befehl eine einzelne Flanke“ · FPGA, VHDL & Co. ·

  • Datei

    tb02cpu2.vhd

    + 1; adreg <= dataIn(5 downto 0); else adreg <= pc; end if; -- ALU / Data Path case states is when "010" => akku <= ("0" & akku(7 downto 0)) + ("0" & dataIn); -- add when "011" => akku(7 downto 0) <= akku(7 downto 0) nor dataIn; -- nor when "101" => akku(8) <= '0'; -- branch not taken, clear carry when others => null; -- instr. fetch, jcc taken (000), sta (001) end case; -- State machine if (states /= "000") then states <= "000"; -- fetch next opcode elsif (dataIn(7 downto 6) = "11" and akku(8)='1

    in „VHDL Grundlagen mininal CPU auf Spartan 6“ · FPGA, VHDL & Co. ·

  • Thread

    Frage zu elsif

    when others => null;-)

    Matz K. schrieb im Beitrag #4193062: > when others => null;-) Nicht ganz, das würde zu einem case-Statement passen. In dem Fall wäre "else" das Zauberwort (oder Default-Zuweisungen für alle Signale vor dem if-Statement, um keine ungewollten

    FPGA, VHDL & Co. ·Herbert · ·23 Antworten

  • Thread

    Enhancing Code Efficiency in C++

    can help the complier; provided the compiler allows contribution. The compiler is the key point when it comes to producing efficient code. Hence the place to go is the compiler.

    program does not need to be slower and bulkier than a C program. Only use the handy language constructs when they are contributing for good.

    Softwareentwicklung ·Greg B. · ·49 Antworten

  • Datei

    lx9_FT245_0.vhd

    lx9_FT245 is port( CLK: in std_logic; D: inout std_logic_vector(7 downto 0); RXF: in std_logic; --when high do not read TXE: in std_logic; --when high do not write RD: out std_logic; WR: out std_logic; SIWU: out std_logic; CLKOUT: in std_logic; OE: out std_logic; PWRSAV: out std_logic; ACBUS8: out std_logic

    in „FPGA zum PC über USB, FX2 oder FT2232H?“ · FPGA, VHDL & Co. ·

  • Datei

    lx9_FT245_0.vhd

    lx9_FT245 is port( CLK: in std_logic; D: inout std_logic_vector(7 downto 0); RXF: in std_logic; --when high do not read TXE: in std_logic; --when high do not write RD: out std_logic; WR: out std_logic; SIWU: out std_logic; CLKOUT: in std_logic; OE: out std_logic; PWRSAV: out std_logic; ACBUS8: out std_logic

    in „FPGA zum PC über USB, FX2 oder FT2232H?“ · FPGA, VHDL & Co. ·

  • Thread

    Kleine Änderung und mein Design läuft nicht mehr :(

    when "0000" => SOUND_A <= "00000000"; when "0001" => SOUND_A <= "00000001"; when "0010" => SOUND_A <= "00000010"; when "0011" => SOUND_A <= "00000011"; when "0100" => SOUND_A

    <= "01011010"; when "1111" => SOUND_A <= "01111111"; when others => null; end case; end if; end process; Mix_A <= Volume_A(3 downto 0); A <= SOUND_A when (Osc_A = '1' and Enable(0) = '0') or (Period_N_Out

    FPGA, VHDL & Co. ·neuling · ·5 Antworten

  • Thread

    Ampelschaltung mit Coolrunner2

    > dec_out <= "100"; when 6 => dec_out <= "110"; when 7 => dec_out <= "110"; when 8 => dec_out <= "001"; when 9 => dec_out <= "001"; when 10 => dec_out <= "001"; when 11 => dec_out <= "001"; when 12 => dec_out <= "001"; when 13 => dec_out <= "001"; when 14 => dec_out <= "001"; when 15 => dec_out <= "001"; when others => dec_out <= "010"; end case; end

    FPGA, VHDL & Co. ·Tobias Reinhard · ·15 Antworten

  • Thread

    Probleme mit Zähler

    0 setzen; when 3 => -- nach dritter Taktflanke -- enb war 0, count muss immernoch 2 sein assert count = "010" report "enb test failed" severity failure; -------------

    '; --dir low schalten (rueckwaerts) when 10 => -- nach [10] Taktflanke -- count muss nun 1->[5] sein (rueckwaerts) assert count = "101" report "ceil test failed" severity failure; when others

    FPGA, VHDL & Co. ·Justus B. · ·1 Antworten

  • Thread

    Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung

    hphone_l <= line_in_l; hphone_r <= line_in_r; nur 0en an den Ausgang zu geben: hphone_l <= (others => '0'); hphone_r <= (others => '0'); --> man hört immer noch die Musik vom IPod über die angeschlossenen Kopfhörer. Sche

    start_fs_tic_f) ) then --nxt_state <= s_read; end if; --***************************** when s_read => nxt_state <= s_idle; end case; end process calc_next_state; -- Auscodierung Ausgaenge; with nxt_state select d_out_reg_ready_f <= '1' when s_read, '0' when s_idle

    FPGA, VHDL & Co. ·itse_me_mario · ·287 Antworten

  • Datei

    spi_master.vhd

    - dw10_cs <= '0'; -- when x"10" => -- dw00_cs <= '0'; -- dw04_cs <= '0'; -- dw08_cs <= '0'; -- dw0c_cs <= '0'; -- dw10_cs <= '1'; -- when others => -- dw00_cs <= '0'; -- dw04_cs <= '0'; -- dw08_cs <= '0'; -- dw0c_cs <= '0';

    in „unklares Signalverhalten eines SPI-Moduls“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    ADCModule.vhd

    downClk6Counter_var : INTEGER range 0 to 3 := 0; VARIABLE barVec : STD_LOGIC_VECTOR(barSteps-1 downto 0) := (others => '0'); VARIABLE count : INTEGER := 0; VARIABLE my_line : line; begin if (rising_edge(clk)) then if(amplifyPhase = '0') then case counter is when 0 => ad_conv_en_var := '0'; spi_clk_en_var := '0';

    in „High Impedence ausprüfen“ · FPGA, VHDL & Co. ·

  • Datei

    random_cellular.vhd

    (left, middle, right : bit) return bit is variable tmp : bit; begin case left & middle & right is when "110" => tmp := '1'; when "101" => tmp := '1'; when "011" => tmp := '1'; when "010" => tmp := '1'; when "001" => tmp := '1'; when others => tmp := '0'; end case; return tmp; end CA; signal pattern_old : bit_vector(0 to 15):= (others => '0'); signal pattern_new : bit_vector(0 to 15):= (others => '0'); signal sync1, set_seed : bit := '0'; signal counter : integer range 0 to 16 := 0; begin --synchronise set_seed by two flip_flops

    in „Warning: XST:2677“ · FPGA, VHDL & Co. ·

  • Thread

    vhdl kontrollstruktur case mit vektoren

    sw0; vec(3) := clk; vec(4) := y1; vec(5) := sw1; case vec is when "--100" => y0 <= '1'; start <= '1'; when "--1-1" => start <= '0'; when "---1-" => y0 <= '0'; when "001--" => y0 <= '1'; start <= '1'; when "101--" => start

    version of case which allows don't care behaviour, case?. Here is an example: case? sel is when "1---" => o <= "11"; when "-1--" => o <= "10"; when "--1-" => o <= "01"; when "---1" => o <= "00"; when others => null; end case; The comparison is carried

    FPGA, VHDL & Co. ·mikrofriendly · ·8 Antworten

  • Thread

    Automat-Anzeigemodul

    -- FSM-process mux: process (dig0, dig1, dig2, dig3, cnt) begin case cnt is when "00" => e <= dig0; when "01" => e <= dig1; when "10" => e <= dig2; when "11" => e <= dig3; when others => e <= 0; end case; end process mux; enc:process(e) begin case e is when 1 => data_array(index)(6 downto 0) <= "0000000"; when 2 => data_array(index)(6 downto 0) <= "0000001"; ... when 128 => data_array(index)(6 downto 0) <= "1111111"

    FPGA, VHDL & Co. ·Adrian · ·11 Antworten

  • Thread

    Logisch High/Low/RTL_EQ/Latch

    arbeiten architecture Behavior of shift_reg is signal QINT: STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); begin shift_reg: process (CLK, Reset) begin if Reset = '1' then Q <= (others => '0'); elsif CLK = '1' and CLK'event then QINT <= D & QINT(7 downto 1 ) ; Q <

    -- 1 -- links .. rechts signal reg : std_logic_vector(7 downto 0):= (others=>'0'); : reg <= DATAIN & reg(7 downto 1) when rising_edge(clk); [/vhdl] Oder so was: [vhdl] -- 2 -- links .. rechts signal reg : std_logic_vector(0 to 7):= (others=>'

    FPGA, VHDL & Co. ·Sin S. · ·11 Antworten

  • Thread

    Fehlermeldung mit unsigned

    "; when "0011" => Sieben_segment_Ausgang(7 downto 1) <= "0000110"; when "0100" => Sieben_segment_Ausgang(7 downto 1) <= "1001100"; when "0101" => Sieben_segment_Ausgang(7 downto 1) <= "0100100

    "; when "1111" => Sieben_segment_Ausgang(7 downto 1) <= "0111000"; when others => Sieben_segment_Ausgang(7 downto 1) <= "0000000"; end case; end process; seg_out <= Sieben_Segment_ausgang

    FPGA, VHDL & Co. ·Andreas Hutstein · ·11 Antworten

  • Datei

    sr_adc4.vhdl

    serial and internal clock process (cs, i_clock) begin if (cs = '0') then aConv <= '0'; odChA <= (others=>'0'); odChB <= (others=>'0'); elsif rising_edge(i_clock) then sCounter <= sCounter + 1; sr <= sr(sr'left-1 downto 0) & aData; case sCounter is when 0 => if (doADC = '1') then aConv <= '1'; end if;

    in „Der vhdl-Schnipsel-Anfängerfragen Thread“ · FPGA, VHDL & Co. ·

  • Datei

    PWM.vhd

    (s_ctr, reset_n) begin if reset_n ='1' then --asynchroner Reset v_o <= '0'; s_led <= (others => '1'); s_state <= IDLE; else case s_state is when IDLE => -- STOP if pause_i = '1' then s_state <= PAUSE; elsif play_i = '1' then s_state <= PLAY; elsif stop_i = '1' or eof_i = '1' then s_state <= IDLE; else s_state <= IDLE; end if; v_o <= '0'; s_ctr <= (others => '0'); s_led <= s_led or "10000000"; when PLAY => if pause_i = '1' then s_state <= PAUSE; elsif play_i = '1' then s_state <= PLAY; elsif stop_i = '1' or eof_i = '1' then s_state <= IDLE; else s_state

    in „HILFE, ich finde nicht raus wo der Fehler liegt!“ · FPGA, VHDL & Co. ·

  • PDF

    Against-Tithing-John-Owen-80.pdf

    and there is no mention therein of the genealogies of the patriarchs who were of that lineage from when e Christ did come ; but when it makes mention of any others, though beginning of his days, or the end of his life. Whatever, therefore they be never so eminent, it reckoned not up their genealogy Thu

    in „OCR-PDFs in epub umwandeln“ · Offtopic ·

  • Thread

    Komische Info von ISE

    ; when R6 => state <= R7; when R7 => state <= idle; when W1 => state <= W2; when W2 => UART_CS <= '1'; state <= W3; when W3 => state <= W4; when W4 => UART_WR <= '1'; state <= W5; when W5 => state <= W6; when W6 => state <= W7; when W7 => state <= idle; when others

    FPGA, VHDL & Co. ·Christian Peters · ·7 Antworten

  • Datei

    mini_merge_data.vhd

    state_output_logic : process(i_reset,i_data_valid_s,w_state_reg,w_index_reg,i_data_s) begin case w_state_reg is when idle => o_state <= (1 => '1', others => '0'); -- validation o_busy <= '0'; if (i_reset = '1') then w_state_next <= idle; w_index_next <= (others => '0'); o_data_long <= (others => '0'); o_next_data

    in „Counter in FSM zählt nach synthese falsch“ · FPGA, VHDL & Co. ·

  • Datei

    SN74HC595_1.vhd

    initcounter +1; else if div < 511 then div <= div +1; else if data_1 /= reg then reg <= data_1; div <= (others => '0'); end if; end if; end if; end process; SN74HC595_1_SER <= reg(to_integer(div(7 downto 5))) when div < 256 else '0'; SN74HC595_1_SRCLK <= div(4) when div < 256 else '0'; SN74HC595_1_RCLK <= '1' when div > 256 and div < 256+20 else '0'; end Behavioral;

    in „Serielle Ausgabe (VHDL)“ · FPGA, VHDL & Co. ·

  • Datei

    lcd.vhd

    - process (pclk, Blank) begin if (Blank = '0') then scount <= (others => '0'); elsif (pclk' event and pclk = '0') then scount <= scount + 1; end if; end process; -------------------------------- -- PixelSel -------------------------------- process (R,G,B, InSel(2 downto 0)) begin case InSel(2 downto 0) is when "000" => sdata <= R; when "001" => sdata <= G; when "010" => sdata <= B; when "011" => sdata <= R AND G AND B; when "100" => sdata <= R OR G OR B; when others => sdata <= '0'; end case; end process;

    in „Fehler im Code, oder am CPLD ?“ · FPGA, VHDL & Co. ·

  • Thread

    Uhr Beschreiben

    --4 when "0101" => LED <="0010010"; --5 when "0110" => LED <="0000010"; --6 when "0111" => LED <="1111000"; --7 when "1000" => LED <="0000000"; --8 when "1001" => LED <="0010000"; --9 when others => LED <="0000110"; -- Error end case; end process; end Anzeige; [/vhdl]

    FPGA, VHDL & Co. ·Flo · ·22 Antworten

  • Thread

    Signal bleibt ständig undefiniert

    normalerweise anders. Nämlich mit einer Typdefinition für die Zustände. Dann braucht man auch keinen /others/ Pfad: http://www.lothar-miller.de/s9y/archives/30-when-others.html Sparxx schrieb im Beitrag #2597797: > Das Signal musst du zuerst initialisieren,es kann ja nicht irgendeinen > Anfangswert

    Übrigens das hier brauchst du nicht,glaube ich: [vhdl]WHEN state_wait => --Wenn im Wartezustand (tür zu, licht noch an) IF sechsSekFlag = '1'THEN folge_zustand <= state_idle; sechsSekFlag <= '0';--hier [/vhdl] denn,sechsSekFlag ist '1' für die dauer

    FPGA, VHDL & Co. ·Stephen Trowbridge · ·12 Antworten

  • Thread

    process immer laufen in VHDL

    <= "000100" & "00" & "00111111"; when 3 => lut_data <= "001001" & "00" & "00100000"; when 4 => lut_data <= "010000" & "00" & "00111111"; when 5 => lut_data <= "010001" & "00" & "00111111"; when 6 => lut_data <= "010010" & "00" & "00101111"; when 7 => lut_data <= "010011" & "00" & "00101111"; when others =>lut_data <= "0000000000000000

    FPGA, VHDL & Co. ·Plau Sein · ·13 Antworten

  • Datei

    Rs232Tx.vhd

    ; end if; end if; end if; when DataBufferBusy => if (BitStrobe = '1') then case (R.Region) is when StopBitAndIdle => NextR.Tx <= cTxLineStopBitAndIdleVal; NextR.DataInputState <= CanAcceptNewData; when StartBit => NextR.BitIdx <=

    in „Xilinx ISE Mehrfach-Instanzierung Bug(?)“ · FPGA, VHDL & Co. ·

  • Thread

    UART-Transmitter-Reset

    -- sensitive to clock, asynch reset by reset -- -- storage data in internal register when data_ready = 1 -- ----------------------------------------------------------- data_storage : process (clk, reset, sent) is begin if reset = '1' or sent then data_register <= (others => '0');

    <= 0; sent <= true; tx_ready_int <= '1'; when others => count_bit <= count_bit + 1; tx <= data_register(count_bit - 1); end case; end if; end if; end process data_send; end architecture behavior;

    FPGA, VHDL & Co. ·Anfänger · ·1 Antworten

  • PDF

    1.0_OLED_REX012864CWAP3N00000_white.603913.pdf

    Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write. Page 7 , Total 27 Pages This is a MPU interface input pad. When connected to an 8080 series MPU, it is active LOW. This pad is connected to the RD signal of the 8080 series MPU, and the data bus is in an output status when this signal is “L”. 17 RDB When connected to a 6800 series MPU , this is active HIGH. This is used as an enable clock input of the 6800 series MPU. When RD = “H”: Enable. When RD = “L”: Disable. 18

    in „SH1106 Init-Sequenz“ · Mikrocontroller und Digitale Elektronik ·

  • Thread

    Quickstart CPLD

    anstatt "count_out <= count_int" folgendes: with count_int select count_out <= "0001" when "00", "0010" when "01", "0100" when "10", "1000" when others; Da siehst Du ja dann ob die LEDs in der richtigen Reihenfolge leuchten.

    -------------------------------------------------- The OFFSET constraint applies only to CPLDs when the clock is on a global clock net. This can be achieved by performing one of the following: 1. Placing the following constraint on the clock net NET myclock BUFG=CLK; (replace myclock with

    FPGA, VHDL & Co. ·Michael · ·20 Antworten

  • PDF

    DTA124E-D.pdf

    Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: 98ASB42226B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOT−23 (TO−236) PAGE 1 OF 2 onsemi and are trademarks of

    in „Bauteil identifzieren“ · Analoge Elektronik und Schaltungstechnik ·

  • Thread

    CRC Berechnung für Ethernet

    > OutByte <= CRCResultInverted( 15 downto 8); SendBufferState <= SendCRC1; when SendCRC1 => OutByte <= CRCResultInverted( 23 downto 16); SendBufferState <= SendCRC2; when SendCRC2 => OutByte <= CRCResultInverted( 31 downto 24); SendBufferState <= SendCRC3; when SendCRC3 => OutByte <= (others => '0'); TXOut <= '0'; SendBufferState <= Idle; [/vhdl] Es gibt noch den Hinweis, dass die ersten 32 Bit der MAC-Adresse invertiert

    FPGA, VHDL & Co. ·Rooney Bob · ·11 Antworten

  • Thread

    Fragen zum VHDL Drehgeber Code

    <= '0'; ce <= '0'; error <= '1'; when "0100" => up_down <= '0'; ce <= '1'; error <= '0'; when "0101" => up_down <= '0'; ce <= '0'; error <= '0'; when "0110" => up_down <= '0'; ce <= '0'; error <= '1'; when "0111" => up_down

    <= '0'; ce <= '0'; error <= '0'; when others => null; end case; end process; [/vhdl] up_down ist im Fehlerfall, bei keiner Bewegung und bei einer Rückwärtsbewegung '0'. Bei der Vorwärtsbewegung ist up_down '1'. ce ist bei keiner

    FPGA, VHDL & Co. ·Reinhard J. · ·6 Antworten

  • Datei

    i2c.vhd

    or previous no-acknowledge ack_error <= '1'; --set error output if no-acknowledge END IF; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; --set sda output WITH state SELECT sda_ena_n <= data_clk WHEN start, --generate start condition NOT data_clk WHEN stop, --generate stop condition sda_int WHEN OTHERS; --set to internal sda signal --set scl and sda outputs scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z'; sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z'; END logic;

    in „De0-Nano Accelerometer: keine Antwort“ · FPGA, VHDL & Co. ·

  • Thread

    Als Ingenieur in die Politik gehen

    "other-oriented" feelings of sympathy and concern for unfortunate others > Personal Distress – measures "self-oriented" feelings of personal anxiety and unease in tense interpersonal settings Mit Fragen wie: "I daydream and fantasize, with some regularity, about

    intelligence is important, but the unbridled enthusiasm has obscured a dark side. New evidence shows that when people hone their emotional skills, they become better at manipulating others. When you’re good at controlling your own emotions, you can disguise your true feelings. When you know what others are feeling

    Ausbildung, Studium & Beruf ·hansi · ·138 Antworten

  • Datei

    Loopback.vhd

    = '1' THEN -- Synchronous reset. state <= s_Idle; s_rx_ack <= '0'; s_tx_ack <= '0'; s_output <= (OTHERS => '0'); s_buffer <= (OTHERS => '0'); ELSE CASE state IS WHEN s_Idle => IF s_rx_rdy = '1' THEN s_buffer <= s_rx_data; -- s_rx_ack <= '1'; state <= s_Read; ELSE s_rx_ack <= '0'; s_tx_ack <= '0'; --s_output <= (others => '0'); --s_buffer <= (others => '0'); END IF; WHEN s_Read => s_rx_ack <= '0'; -- Debug! (Lothar M.) s_output <= x"55"; state <= s_Write; -- End Debug! -- Vereinfachte Dekodierung in Kommando/Datenbyte

    in „UART Kommandos funktionieren nicht“ · FPGA, VHDL & Co. ·

  • Datei

    SR_24Bit.vhd

    <= Counter +1; else if Start = '1' then TX_Reg <= Data; Counter <= (others => '0'); end if; end if; end process; Ready <= '1' when Start = '0' and Address > 25 else '0'; TX <= TX_Reg(to_integer(Address)) when Address < 24 else '0'; ShiftCLK <= Counter(3) when Address < 24 else '0'; LatchCLK <= '1' when Address = 25 else '0'; end Behavioral;

    in „Serielle Ausgabe (VHDL)“ · FPGA, VHDL & Co. ·

  • Thread

    latch ?

    <= s4; when s4 => next_state <= s1; end case; end process process2; process3 : process (state) begin case state is when s1 => outp <= '1'; when s2 => outp <= '1';

    VHDL] signal DATA : std_logic_vector(15 downto 0) ; . . process(DATA,ACK, ... ) . DATA <= (others => '0'); . case xx is . . when DATA_H => ADDR <= "0"; if ACK = '1' then DATA(15 downto 8) <= DATA_IN; end if; when DATA_L => ADDR <

    FPGA, VHDL & Co. ·chris · ·7 Antworten

  • Thread

    VHDL - 'Warnung' vom Synthesetool (Synplify) unverständlich

    : CL275 :"D:\test\test2\hdl\Test.vhd":42:11:42:11|Possible don't care specified as next state in others or default clause, or failure to extract state machine @END Der VHDL-Code dazu: [vhdl] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- library proasic3; entity Testprojekt

    after 2 ns; else z <= z + 1 after 2 ns; end if; case z is when 1 => out_vec <= b"0001"; when 2 => out_vec <= b"0010"; when OTHERS => out_vec <= b"1001"; end case; -- if (z = 1) then -- out_vec

    FPGA, VHDL & Co. ·Andreas Ramert · ·14 Antworten

  • Thread

    Lauflicht mit CPLD

    (clk) then cnt <= cnt+1; end if; end process; process(cnt) begin case cnt is when "000" => led <="00000001"; when "000" => led <="00000010"; when "000" => led <="00000100"; when "000" => led <="00001000"; when "000" => led <="00010000"; when "000" => led <="00100000"; when "000" => led <="01000000"; when "000" => led <="10000000"; when others => null; end case; end process; [/vhdl] MFG Falk

    FPGA, VHDL & Co. ·D. E. · ·9 Antworten