Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    log2.vhd

    ! logzero <= '1'; dout <= (others => '0'); drdy <= '1'; else state := STATE_SHIFT; sr := din; end if; end if; when STATE_SHIFT => if sr(15) = '1' then ram_addr <= sr(14 downto 7); state := STATE_LUT; else sr := sr(14 downto 0) & '0

    in „Logarithmus in VHDL“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL Signal Teilen und in die nächst höhere Adresse schreiben

    Adresse. Ich bekomme folgende Fehlermeldung: The data cannot be written to the memory correctly when only en_write is enabled, or the content of memory cannot be read. Kann mir jemand sagen, wo mein Problem liegt? Mein RAM [vhdl]library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all

    downto 0); type ram_type is array (1023 downto 0) of logic_vector; signal ram : ram_type := ((others=> (others=>'0'))); begin process(Clk) begin if(en_read = '1') then outputsignal <= ram(to_integer(unsigned(addr2))); elsif(en_write = '1') then input_1 <= input(17 downto 0); input

    FPGA, VHDL & Co. ·Markus G. · ·12 Antworten

  • Thread

    nach Kündigung Auszeit & Selbststudium J2EE?

    http://programmers.stackexchange.com/questions/25564/when-should-you-call-yourself-a-senior-developer You can call yourself a Senior when: - You can handle the entire software development life cycle, end to end - You lead others, or others look

    person will leverage asynchronous programming, queuing, caching, logging, security and persistence when appropriate. When asked they can give a detail explanation of their choice and the pros and cons. In most cases they have mastered object oriented programming and design, this not an absolute other

    Ausbildung, Studium & Beruf ·Roland Kr. · ·44 Antworten

  • Thread

    Verhalten Sim vs Post Fit Sim

    when "0011" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1'; when "0100" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0'; when "0101" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0';

    when "1111" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0'; when others => null; end case; end if; end if; end process QDecoder; end VERH;[/vhdl] nicht korrekt synthetisiert

    FPGA, VHDL & Co. ·AlexW · ·5 Antworten

  • Datei

    ALU.vhd

    " => Y <= YMulti; when "0100" => Y <= NOT Ob; when "0101" => Y <= Oa AND Ob; when "0110" => Y <= Oa OR Ob; when "0111" => Y <= Oa XOR Ob; when "1000" => Y <= Oa NAND Ob; when "1001" => Y <= Oa NOR Ob; when "1010" => Y <= Oa XNOR Ob; when "1011" => Y <= Ob + 1; when "1100" => Y <= Ob - 1; when "1101" => NULL; when others => NULL; end case; end process; end Behavioral;

    in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·

  • Datei

    fsm.vhd

    (taster(8) = '1') then next_state <= S9; end if; when S9 => if (timer = 0) then next_state <= S0; end if; end case; end process; process(next_state) begin case next_state is when S0 => led <= (others => '1'); when S1 => led <= "11000000"; when S2 => led <= "11100000"; when S3 => led <= "11110000"; when S4 => led <= "11111000"; when S5 => led <= "11111100"; when S6 => led <= "11111111"; when S7 => led <= "00000011"; when S8 => led <= "00000111"; when S9 => led <= (others

    in „Automaten(FSM) und die verschiedenen Prozess Modelle“ · FPGA, VHDL & Co. ·

  • Datei

    Enigma.vhd

    found : boolean; begin read_write : process (clock, reset, init) begin if reset = '1' then rotor <= (others => (others => '0')); elsif init = '1' then position <= rotor'left; elsif rising_edge(clock) then if write_enable = '0' and read_enable = '1' and lookup = '1' then found <= false; -- Search all entries

    in „Fehler im Design“ · FPGA, VHDL & Co. ·

  • Datei

    framewrapper.vhd

    <= '1'; end if; when SEND_BOF => sig_disconnected <= '0'; READ_TX_FIFO <= '1'; sig_send_bof <= '0'; sig_write_uart <= '1'; -- var_state := SEND_DATA; -- end if; when SEND_DATA => if sig_no_more_data = '1' then -- READ_TX_FIFO

    in „State Machine: undefinierter Zustand.“ · FPGA, VHDL & Co. ·

  • Datei

    framewrapper.vhd

    <= '1'; end if; when SEND_BOF => sig_disconnected <= '0'; --READ_TX_FIFO <= '1'; sig_send_bof <= '0'; -- sig_write_uart <= '1'; var_state := SEND_DATA; when SEND_DATA => if sig_no_more_data = '1' then READ_TX_FIFO <= '0

    in „State Machine: undefinierter Zustand.“ · FPGA, VHDL & Co. ·

  • Thread

    FSM Automat(für bestimmte zeit in einem zustand bleiben)

    bar aber ich will da bleiben counter<=(others=>'0');--für bestimmte zeit Folge_z<=S4; end if; . . . MFG

    counter <= (others => '0'); --für bestimmte zeit Folge_z <= S4; end if; [/vhdl] Was sagen den Folge_z und counter in der Simulation? Rick

    FPGA, VHDL & Co. ·VHDL_Bginner · ·4 Antworten

  • Thread

    2x werden die Daten 128-254 ausgegeben vom SRAM statt 0-254, woran liegt das bitte ?

    txd => txd, tx_start => tx_start, tx_data => tx_data ); sram_io <= data_write when read_write='0' else (others=>'Z'); data_read <= sram_io; ub <= '0'; lb <= '0'; process (clk) begin if rising_edge (clk) then if (zustand = "001") then sram_adr <= sr_adr

    rx_data; zustand <= "001"; end if; if sw(0) = '1' then sram_io <= (others => 'Z'); sram_adr <= (others => '0'); we <= '1'; ce <= '1'; oe <= '1'; end if; if sw(1) = '1' then sr_adr <= (others => '0');

    FPGA, VHDL & Co. ·peter · ·4 Antworten

  • Datei

    Rs232Rx.vhd

    iDataRead : in std_ulogic; -- data was read from internal fifo oErrFlag : out std_ulogic); -- set when receiving error occurs, disabled when receiving continues end entity Rs232Rx; architecture RTL of Rs232Rx is type aRs232RxFifo is array (0 to gRxFifoSize-1) of std_ulogic_vector(gBitWidth-1 downto 0

    in „Xilinx ISE Mehrfach-Instanzierung Bug(?)“ · FPGA, VHDL & Co. ·

  • Thread

    2 ATMega8 über SPI kommunizieren lassen

    Mhz */ #endif #include <util/delay.h> void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDRB = (1<<PB4)|(1<<PB0); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void) { /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register

    be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another Master selecting the SPI as a Slave and starting to send data to it.

    Mikrocontroller und Digitale Elektronik ·Erich · ·18 Antworten

  • Datei

    uart_rx.vhd

    ) THEN IF rst = '1' THEN -- Synchronous reset. s_clk_count <= 0; s_bit_index <= 0; s_rx_data <= (OTHERS => '0'); s_rx_rdy <= '0'; state <= S_Idle; ELSE CASE state IS WHEN S_Idle => IF (s_shiftreg(1) <= '0') THEN -- Start bit detected. state <= S_Rx_Start_Bit; s_rx_rdy <= '0'; ELSE state <= S_Idle; END

    in „UART Kommandos funktionieren nicht“ · FPGA, VHDL & Co. ·

  • Thread

    Synchroner Reset in Kombinatorik

    (shift, reset, load, data, enable) begin if reset ='1' then shift_next <= (others => '0'); elsif load = '1' then shift_next <= data; elsif enable = '1' then shift_next <= std_logic_vector(SHIFT_LEFT(unsigned(shift), 1)); else shift_next

    mit Kombinatorik gelöst ist. (nicht zu hause nachmachen, dies ist KEIN Reset): [vhdl] s_out <= (others => '0') when reset = '1' else shift(3); [/vhdl]

    FPGA, VHDL & Co. ·EinVolvic · ·7 Antworten

  • Thread

    Wie designe ich dieses case am besten?

    habe eine verzweigte if-case-Anweisung in dieser Form: [vhdl] if RW = '0' then case DP_M is when "0000" => blabla when "0001" => blabla, etc end case; else case DP_M is when "0000" => blabla when "0001" => blabla, etc end case; [/vhdl] Ich habe also in beiden Fällen (also

    Compiler mitteilen kannst, daß bestimmte Kombinationen nicht relevant sind, z.B. case Adr is when "00" => Data <= "0000"; when "01" => Data <= "0100"; when others => Data <= "----"; -- don't care end case; Grüße Klaus

    FPGA, VHDL & Co. ·Christian Peters · ·7 Antworten

  • Thread

    LCD von TerAsic mit Cyclone II von Altera

    lut_data <= "001001" & "00" & "00100000"; when 4=> lut_data <= "010000" & "00" & "00111111"; when 5=> lut_data <= "010001" & "00" & "00111111"; when 6=> lut_data <= "010010" & "00" & "00101111"; when 7=> lut_data <= "010011" & "00" & "00101111"; when others=> lut_data <= "000000" & "00" & "00000000"; end case; im controller.vhd werden die bits von vorne abgeselen: if (mst < 17) then mst <= mst+1; end if; if (mst < 16) then

    FPGA, VHDL & Co. ·Plau Sein · ·8 Antworten

  • Datei

    taschenrechner.vhd

    1'; --release code, nächste taste ignorieren when X"F0" => kybignore <= '1'; when others => end case; else --E0 ist zur unterscheidung Numblock gut. if ( kybreg /= X"E0" ) then kybignore <= '0'; end if; end if; kybstate <= waitidle; end if; when waitidle

    in „VHDL Rechner“ · FPGA, VHDL & Co. ·

  • Datei

    RS232_Mux.vhd

    -- stop2 when others => if(BaudTick='1') then state <= "0000"; end if; end case; end process; process (state,TxD_dataD) begin case state(2 downto 0) is when "000" => muxbit <= TxD_dataD(0); -- bit 0 when "001" =>

    in „Übersetzung Verilog -> VHDL“ · FPGA, VHDL & Co. ·

  • Datei

    Anzeige.vhd

    ; end if; end if; counter<=counter+"0000000000001"; if(counter > "1000000000000") then counter<=(others=>'0'); end if; end if; end process; Anzeigen: process(code) begin case code is when "0000" => LED <="1000000"; --0 when "0001" => LED <="1111001"; --1 when "0010" => LED <="0100100"; --2 when "0011

    in „Uhr Beschreiben“ · FPGA, VHDL & Co. ·

  • Datei

    top_sub_melodyPlayer.vhd

    not "10000000" , "000" when others ; -- melody2 with sequencerStep select note2 <= "000" when not "00000001" , "010" when not "00000010" , "101" when not "00000100" , "011" when not "00001000" , "101" when not "00010000" , "010" when not "00100000" , --"010" when not "01000000" , --"011" when not "10000000" , "000" when others ; end architecture;

    in „VHDL Grundlagen Tonerzeugung“ · FPGA, VHDL & Co. ·

  • Thread

    Externens Ram statt FPGA RAM

    we => ram_we ); end generate; Meine nicht funktionierende Lösung: ram_io <= RWD when ram_wr = '0' else (others => 'Z'); ram_a(12 downto 0) <= RAB; ram_a(19 downto 13) <="0000000"; ram_ce<='0'; ram_oe<='0'; ram_we <= ram_wr;

    dem externen SRAM nachbilden können. > Meine nicht funktionierende Lösung: > ram_io <= RWD when ram_wr = '0' else (others => 'Z'); > ram_a(12 downto 0) <= RAB; > ram_a(19 downto 13) <="0000000"; > ram_ce<='0'; > ram_oe<='0'; > ram_we <= ram_wr; Das ist der Ansatz, es fehlt aber ncoh ne

    FPGA, VHDL & Co. ·Dirk · ·36 Antworten

  • Datei

    I2S_Top.vhd

    STD_LOGIC := '0'; signal TransmitData : STD_LOGIC_VECTOR(0 to ((DATA_WIDTH_PER_CHANNEL * 2) - 1)) := (others => '0'); -- Signal for Audio ROM signal ROM_Data : STD_LOGIC_VECTOR(0 to (DATA_WIDTH_PER_CHANNEL - 1)) := (others => '0'); signal ROM_Address : STD_LOGIC_VECTOR(6 downto 0) := (others => '0'); begin

    in „CS4344 I2S Transmitter“ · FPGA, VHDL & Co. ·

  • Thread

    DCM und Ram Simulieren

    '0'; signal reset_b : std_logic := '0'; signal dina : std_logic_vector(24 downto 0):= (others => '0'); signal addra : std_logic_vector(9 downto 0) := (others => '0'); signal wea : std_logic_vector(0 downto 0) := (others => '0'); begin -- dut -- component instantiation

    BLK_MEM_GEN_V3_3.vhd DEBUG auf 1 setzen und mit Modelsim neu compilieren (memory_i <= memory when DEBUG=1;)

    FPGA, VHDL & Co. ·Fresh · ·28 Antworten

  • Thread

    Post-Map simulation mit ModelSim

    overloaded matching definition for "+" Die zeilen 488..492 -- vsptr_out:SLV((adrbit-1) DOWNTO 0):=(OTHERS => '0'); IF (vsptr_inp = maxbuf) THEN -- Bufferpointer inkrem. vsptr_inp := (OTHERS => '0'); ELSE vsptr_inp := vsptr_inp + '1';--zeile 491 END IF; ist mir völlig unklar wo das fehler sein

    -- vsptr_inp:SLV((adrbit-1) DOWNTO 0):=(OTHERS => '0'); für inp ist die gleiche Definition Gruss Anton

    FPGA, VHDL & Co. ·Anton K. · ·148 Antworten

  • Datei

    toplevel.vhdl

    false; if linectr >= 310 then linectr <= 0; else linectr <= linectr + 1; end if; case linectr is when 309 => vsync <= true; when 2 => vsync <= false; when others => null; end case; else pixelctr <= pixelctr + 1; newline <= '0'; case pixelctr is -- start of sync when 18 => hsync <= true; -- end of sync

    in „Active-HDL: wie bekomme ich die Waveform angezeigt“ · FPGA, VHDL & Co. ·

  • Thread

    Xilinx Latch Problem

    ; when others => null; end case; end process p_memless; p_memzing : process (CLKxCI, RSTxRBI) begin -- process p_memzing if RSTxRBI = '0' then

    heutzutage breite Bildschirme haben, bietet sich 'concurrent' geradezu an: [vhdl] InputDstRdyxS <= '1' when STATExDP = waitforSrc else '0'; [/vhdl] [vhdl] STATExDN <= waitforSrc when STATExDP = reset else count when STATExDP = waitforSrc and InputSrcRdyxS = '1' else

    FPGA, VHDL & Co. ·finalcu · ·8 Antworten

  • Datei

    I2S_tx.vhd

    " else '1'; -- stretching txd signals for QSM mode l_txd <= l_txd_i or l_txd_reg when mclk_sel = '0' else l_txd_i; r_txd <= r_txd_i or r_txd_reg when mclk_sel = '0' else r_txd_i; mclk_div <= to_unsigned(4, mclk_div'length) when sr_sel_reg(3) = '1' else to_unsigned(3, mclk_div'length) when sr_sel_reg(2) = '1' else to_unsigned(2, mclk_div'length) when sr_sel_reg(1) = '1' else to_unsigned(1, mclk_div'length) when sr_sel_reg(0) = '1' else to_unsigned(1, mclk_div'length); -- MCLK/LRCLK =

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    FSM.txt

    prüfen else zustand <= Z14; end if; when Z13 => zustand <= Z14;--Fehler when Z14 => zustand <= Z9; --Fertig when others => zustand <= Z1; end case ; end if; end process FSM; -- Ausgangsmatrix der FSM***************************************

    in „FSM verliert aktiven zustand“ · FPGA, VHDL & Co. ·

  • Datei

    arcCosFP.vhd

    RANGE 0 TO 7:= 0; BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN state <= 0; cntrclk := 0; --(OTHERS => '0'); ELSE CASE state IS WHEN 0 => IF ceacos = '1' THEN ce1 <= '1';-- start für 1-x, x`2, ComP0.5 state <= 1; ELSE state <= 0; END IF; WHEN 1 => --- Ausführen 1-x,X`2,CompX ce1 <= '0'; ce2 <= '1

    in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. ·

  • Thread

    Instruktion SLLI (Shift logical left i times)

    " => m := 64; when "0111" => m := 128; when "1000" => m := 256; when "1001" => m := 512; when "1010" => m := 1024; when "1011" => m := 2048; when "1100" => m := 4096; when "1101" => m := 8192; when "1110" => m := 16384; when others => m := 32768; end case; y <= std_logic_vector(unsigned(a) * m); end process; [/vhdl] Number of Slices

    FPGA, VHDL & Co. ·Unnormaley · ·4 Antworten

  • Thread

    Bereich abprüfen

    [vhdl] process (clk) begin if rising_edge(clk) then case pixel is when 0 => X <= "0001"; when 80 => X <= "0010"; when 160 => X <= "0011"; when 240 => X <= "0100"; when 320 => X <= "0101"; when 400 => X <= "0110"; when 480 => X <= "0111"; when others => X <= X; -- sonst Wert halten end case; end if; end process; [/vhdl]

    FPGA, VHDL & Co. ·Miriam · ·4 Antworten

  • Datei

    moore.vhd

    next_state; end if; end if; end process; output_decode : process(state, yout_int) begin case(state) is when Idle => yout_int <= '0'; when A1 => when B1 => when C1 => when A11 => yout_int <= '0'; when B11 => yout_int <= '1'; when C11 => yout_int <= not yout_int; when others => yout_int <= '0'; end case; end

    in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. ·

  • Thread

    Ein wirklich blöder Fehler, den ich nicht sehe

    is port( BTN : in std_logic; LED : out std_logic_vector(7 downto 0) := (others => '0') ); end entity Debounce_Test; [/vhdl] das "(others => '0')" macht hier etwas völlig anderes, als anscheinend von allen angenommen. Am dichtesten dran (aber immer noch auf dem Holzweg

    LED <= (cnt => '1', others => '0'); -- end process; -- -- Diamond: Err choice is not constant / XST Err: Choices must be locally static -- -- ISIM: statisch "00100000" -- LED <= (cnt => '1', others => '0'

    FPGA, VHDL & Co. ·Erik · ·167 Antworten

  • Thread

    SPI und SCK Problem

    die Initialisierung des SPI: [c] DDRB = (1<<PB5) | (1<<PB7); //Set MOSI and SCK output, all others input DDRB |= (1<<PB4);// configure the CS Pin as output as not to affect the SPI /* initialize SPI Control Registers */ SPCR |= (1<<SPE); //enables SPI functionality SPCR &= ~(1<<

    *** ENDE sei(); DDRB = (1<<PB5) | (1<<PB7); //Set MOSI and SCK output, all others input DDRB |= (1<<PB4); // configure the CS Pin as output as not to affect the SPI /* initialize SPI Control Registers */ SPCR |= (1<<SPE); //enables SPI functionality

    Mikrocontroller und Digitale Elektronik ·Jakob M. · ·26 Antworten

  • Datei

    vga.vhd

    else ball_x_s <= ball_x_s - vx_s; end if; end case; case state_y is when down => if ( ball_y_s > 600-20-vy_s ) then ball_y_s <= 600 - 20; state_y <= up; else ball_y_s <= ball_y_s + vy_s; end if; when up => if ( ball_y_s < vy_s ) then ball_y_s <= 0; state_y <= down; else

    in „vga Ausgabe - was bremst denn da.“ · FPGA, VHDL & Co. ·

  • Datei

    NiosII_ADXL345_spi_read.vhd

    std_logic_vector(7 downto 0); -- export switch_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export gpio_external_connection_export : inout std_logic_vector(31 downto 0) := (others =>

    in „DE0_Nano ADXL345 SPI“ · FPGA, VHDL & Co. ·

  • Thread

    Taschenrechner in VHDL

    variable zahl: unsigned(15 downto 0); Begin case state_zahl is when zahl1_state => zahl(3 downto 0) := unsigned(eingabe); state_zahl <= zahl2_state; when zahl2_state => zahl := shift_left(zahl

    downto 0) := unsigned(eingabe); state_zahl <= zahl1_state; when others => state_zahl <= zahl1_state; end case; ausgabe(15 downto 0) <= std_logic_vector(zahl); end process verarbeitung; [/vhdl]

    FPGA, VHDL & Co. ·andreas · ·25 Antworten

  • Thread

    Adder/Subtracter Map Problem

    architecture Behavioral of AdderSubtracter is begin y <= STD_LOGIC_VECTOR(UNSIGNED(a)+UNSIGNED(b)) when sel = "00" else STD_LOGIC_VECTOR(SIGNED(a)+SIGNED(b)) when sel = "01" else STD_LOGIC_VECTOR(UNSIGNED(a)-UNSIGNED(b)) when sel = "10" else STD_LOGIC_VECTOR(SIGNED(a)-SIGNED(b)) when sel = "11" else (others => '0'); end Behavioral; ----------------------------------------------- [/vhdl] Die Constaints Datei sieht so aus: [vhdl] ######################

    FPGA, VHDL & Co. ·Samer Afach · ·9 Antworten

  • PDF

    vhdl.pdf

    statement a 00 good case: process (a, b, c, d, sel) b 01 begin −− process bad if c 10 case sel is d 11 when ”00” => o <= a; when ”01” => o <= b; sel when ”10” => o <= c; when others => o <= d; Use case statement for end case; multiplexers end process good case; Best synthesis results Hardware Design with

    in „Synthesefähiger Code“ · FPGA, VHDL & Co. ·

  • Thread

    VIVADO 2017.1

    aber 2016.4: ERROR: [VRFC 10-2335] selected assignment statement does not cover all choices. 'others' clause is needed [D:/vhdl/TEM_uni_5_stream/TEM_uni_5_stream.srcs/sources_1/TEM_uni_5_adc_stream.vhd:206] [vhdl]with ADC_select select ADC_data <= fifo_counter when "000", AD7356_1_data when "001", AD7356_2_data when "010", AD7356_3_data when "011", AD7356_4_data when "100", AD7356_5_data when "101", AD7356_6_data when "110", fifo_counter when "111";[/vhdl]

    FPGA, VHDL & Co. ·Gustl B. · ·23 Antworten

  • Thread

    Open Bench Logic Sniffer - FPGA läuft nicht an

    reset_shreg(reset_shreg'left); if async_reset = '1' then reset_shreg <= (others => '1'); end if; end process; reset_n <= not reset; [/vhdl] Duke

    do mention to try another USB cable or even another USB Port. But as you have the strange error when mounting it in a case , i'd say a solder defect on the board. /Bingo

    FPGA, VHDL & Co. ·Wolfgang M. · ·19 Antworten

  • Datei

    gitarre.vhd

    <= "1011" ; when others => dsp_puffer <= freq_puffer(15 downto 12) ; enable <= "0111" ; end case ; case dsp_puffer is when "0000" => seg <= "0000001"; when "0001" => seg <= "1001111"; when "0010" => seg <= "0010010"; when "0011" => seg <= "0000110"; when "0100" => seg <= "1001100"; when "0101" => seg <= "0100100"; when "0110" => seg <= "0100000"; when "0111" => seg <= "0001111"; when "1000" => seg <= "0000000"; when

    in „Frequenzzähler+bad synchronous description.“ · FPGA, VHDL & Co. ·

  • Datei

    gitarre_neu.vhd

    <= "1011" ; when others => dsp_puffer <= freq_puffer(15 downto 12) ; enable <= "0111" ; end case ; case dsp_puffer is when "0000" => seg <= "0000001"; when "0001" => seg <= "1001111"; when "0010" => seg <= "0010010"; when "0011" => seg <= "0000110"; when "0100" => seg <= "1001100"; when "0101" => seg <= "0100100"; when "0110" => seg <= "0100000"; when "0111" => seg <= "0001111"; when "1000" => seg <= "0000000"; when

    in „Frequenzzähler+bad synchronous description.“ · FPGA, VHDL & Co. ·

  • Datei

    gitarre_neu.vhd

    <= "1011" ; when others => dsp_puffer <= freq_puffer(15 downto 12) ; enable <= "0111" ; end case ; case dsp_puffer is when "0000" => seg <= "0000001"; when "0001" => seg <= "1001111"; when "0010" => seg <= "0010010"; when "0011" => seg <= "0000110"; when "0100" => seg <= "1001100"; when "0101" => seg <= "0100100"; when "0110" => seg <= "0100000"; when "0111" => seg <= "0001111"; when "1000" => seg <= "0000000"; when

    in „Frequenzzähler+bad synchronous description.“ · FPGA, VHDL & Co. ·

  • Datei

    atanFP.vhd

    rising_edge(clk) THEN IF nrst = '0' THEN stateatan <= 0; cntrclk := 0; cecomp <= '0'; sign := "00"; --(OTHERS => '0'); ELSE CASE stateatan IS WHEN 0 => IF ceatan = '1' THEN IF (Yinp = X"00000000") AND (Xinp = X"00000000") THEN atanFP <= X"00000000"; stateatan <= 0;-- ungültige wert ELSE stateatan <= 1; END

    in „Post-Map simulation mit ModelSim“ · FPGA, VHDL & Co. ·

  • Thread

    If und Port-Map Problem

    1100110"; when "0101" => led <= NOT "1101101"; when "0110" => led <= NOT "1111101"; when "0111" => led <= NOT "0000111"; when "1000" => led <= NOT "1111111"; when "1001" => led <= NOT "1101111"; when others => led <= "ZZZZZZZ"; end case; end if; end process; end behv; ------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use

    FPGA, VHDL & Co. ·FPGA_Beginner · ·7 Antworten

  • Thread

    State Machine mit 2 Clocks

    States.) [c] --state machine process. process (current_s,input) begin case current_s is when ready => --when current state is "ready" output <= '0'; if(input ='1') then next_s <= steady; else next_s <= ready; end if; when steady =>;

    change. end if; end process; process (clk1,clk2,current_s) is begin case current_s is when ready => clk_temp <= clk1; when steady => clk_temp <= clk2; when others => clk_temp <= clk1; end case; end process; [/c] Bernd

    FPGA, VHDL & Co. ·Bege · ·9 Antworten

  • Thread

    1-Bit-Komparator als Komponente für n-Bit-Komparator

    --Hilfsvektor END GENERATE SCHLEIFE; --Größer ZOUT(2) <= '1' WHEN Hi>Lo ELSE '0'; --Gleich ZOUT(1) <= '1' WHEN Eq=EqH ELSE '0'; --Kleiner ZOUT(0) <= '1' WHEN Lo>Hi ELSE '0'; end architecture verhalten;

    Da ich keine "=" Operation beim std_logic_vector > machen konnte, sonst ginge ja: Ausgang <= '1' WHEN Vector = (N-1); Ausgang <= '1' WHEN Vector = (others => '1'); sollte gehen. Für beliebige integer geht es auch, mit ein paar Typumwandlungen. Je nachdem, welche library du für std_logic verwendest

    FPGA, VHDL & Co. ·Float · ·22 Antworten

  • Datei

    HuffmanLu_encode.vhd

    ((DC_ADD_Code),7); index_a <= 13; when 8 => out_reg_a(95 downto 89) <= "1111110"; out_reg_a(88 downto 81) <= conv_std_logic_vector((DC_ADD_Code),8); index_a <= 15; when 9 => out_reg_a(95 downto 89) <= "1111111"; index_a <= 7; when others

    in „Xilinx ISE XST Probleme“ · FPGA, VHDL & Co. ·