Zeitraum zwischen dem Anschwellen und Abklingen des Impulses auf jeweils die Hälfte des Maximalwertes: 1.3 A m 1.2 i 1.1 d 1.0 e 0.9 0.8 0.7 0.6 T 0.5 0.4 0.3 0.2 0.1 t in [µs] 0.0 -0.1 -0.2 . 0.5 . 5.0 . 0.5 . 5.0 . . . . . . 5. . 5.0 . . . 5.0 . 0.5 . 5.0 . 0.5 . . . . - 3-3 - 2-2 - 2-1 - 1-17-5 - 0-
sheet.getCellByPosition(6,4).string = channel_name REM ++++++++ calculate y resolution ++++++++++++++ get #1,8,raw_data select case raw_data case 0 y_per_div = 20 y_unit="mV" case 1 y_per_div = 50 y_unit="mV" case 2 y_per_div = 100 y_unit="mV" case 3 y_per_div = 200 y_unit="mV" case 4 y_per_div = 500 y_unit
hp running-auto triggering
CHANNEL 1 2 3 4
off on
100 mV/div
offset 0.00000 V
dc ec BW lim LF rej
-50.0000 us 0.00000 s 50.000 us
realtime
10.0 us/div
more preset probe
y2(1) 64.000mV x2(1) 400.000us
y1(1) -64.000mV x1(1) -404.000us
delta y 128.000mV delta x 804.000us
1.24378kHz
version - L.Westlund ;1.1 - Added data alignment for TI_year - D. Szmulwicz ; - Changed US Daylight savings time algorithm ;****************************************************************************** ;Variables .def TI_day
Trig'd A H1 Period 23,66 us Frequency 42,26 kHz Vpp 40,00 mV +PulseWidth 12,65 us -PulseWidth 10,85 us Vrms 11,27 mV H2 ? 104,0 mV 14,15 us 9,250 us 27,96 mV C 50 mV/div AC 200 mV/div 0.28divs 1.92divs S 34779 kHz M 10us/div T 0.0 ns D 5k Trigger Force 4,000 mV
der Systemdeterminante 1 2 M7 Der Kondensatormotor 16 Z1 Z 2 XC Det(N) mit (Z1 Z 2 j2ü ZsZ 1 2 erhalten wir jüsZ 1 X /C s jüsZ 2X /üC s üs mit 1 U Z 2 1 Z 1 U Netz I1 Netz , I 2 U Netz jüsZ 2 X
-2 CN2-2 P D2 rt MBRS130LT3 30509 S CN1-2 CN1B-1 MBRS130LT3 Kabel Endschalter D D 1 2 3 4 P 3TL031SRB M 2D 1 3TL031SRB M Endschalter US3 1 R4 US2 S CN1B ST1 T N 10 9 2 1 9 C L OP2- XTA2 1 1 5 5 2 5 2 2O S 3 1 4 4 3 S3 2 1H2 NP 4 3 O 3 8 1 T4 C- 7 6 B 9 4 1 T 2 6 5 N 51 2 3H1 A 6 5 O ATX-2POLB C S R2 2 0 n 3 0 US1 3 S 0 DIN-8POLS C R 1 10 L 3 Endschalter 1 3TL031SRB M 3 S 3 1 D R D4 B M P
SIGLENT Trig'd M 1.00us/ Delay:0.00s f = 23.5984kHz 2025-04-02 16:27:36 Sa 1.00GSa/s Curr 14.0kpts Edge AC CH1 L 0.0V 1 DC1M 1X 100mV -1.100V ΔX = 7.00us 1/ΔX = 142.9kHz X2 = 3.50us X1 = -3.50us 100mV/ MESSEN Sp.-Sp.[1]=120.00mV Per.[1]=1.03us Quelle K1 Typ Löschen Statistik Aus Übersicht Aus Gate
Built in voltage booster Voltage Doubler V Reference Voltage OUT Vss VD2 CAP1M Voltage Doubler Reference Voltage CAP1P VD2 CAP2M CAP2P CAP3M V SS VOUT VOUT External reset timing VDD Tres XRESET Trw XRESET pulse width Trw 10us RESET start time Tres 50ns V4.0 36/49 2008/08/18 ST7920
Built in voltage booster Voltage Doubler V Reference Voltage OUT Vss VD2 CAP1M Voltage Doubler Reference Voltage CAP1P VD2 CAP2M CAP2P CAP3M V SS VOUT VOUT External reset timing VDD Tres XRESET Trw XRESET pulse width Trw 10us RESET start time Tres 50ns V4.0 36/49 2008/08/18 ST7920
Built in voltage booster Voltage Doubler V Reference Voltage OUT Vss VD2 CAP1M Voltage Doubler Reference Voltage CAP1P VD2 CAP2M CAP2P CAP3M V SS VOUT VOUT External reset timing VDD Tres XRESET Trw XRESET pulse width Trw 10us RESET start time Tres 50ns V4.0 36/49 2008/08/18 ST7920
,high(RAMEND) out SPH,R16 ldi temp,0b11111111 ;Setze I/O Direction an PortB out DDRB,temp ;0=Input 1=Output ldi temp,0b11111111 ;Setze I/O Direction an PortC out DDRC,temp ;0=Input 1=Output ldi temp,0b00000000 ;Setze I/O Direction an PortD out DDRD,temp ;0=Input 1=Output sei ;Interrupts allgemein aktivieren
1.9 V Low input voltage, other pins Vai 1.5 V High input voltage , other pins Vaih 3.5 V L,M,R input current ( pull low resistor, Vin=5V ) Imi 35 45 uA DATA, CLK input current Idc -0.6 -1.86 mA ( pull up resistor, Vin=0V ) DATA, CLK low output voltage ( Iprl=4mA ) Vprl 0.4 V OSC IN input leakage current (Vin=5V) Iih 0 1.0 uA L,M,R input leakage current ( Vin =0V ) Iil -1 1 uA X1, X2,Y1,Y2,Z1,Z2 input leakage current (Vin=0V) Iipl -1 1 uA Input resistor of button
SIGLENT Auto M 1.00us/ Delay:0.00s f < 10Hz 2025-04-02 16:26:58 Sa 1.00GSa/s Curr 14.0kpts Edge CH1 AC L 0.0V 1 DC1M 1X 100mV -500mV ΔX = 7.00us 1/ΔX = 142.9kHz X2 = 3.50us X1 = -3.50us MESSEN Sp.-Sp.[1]=16.00mV Per.[1]=2.29us Quelle K1 Typ Löschen Statistik Übersicht Gate Aus Aus
V =3.6V η 效率 DD 90 % RL=4Ω, (Class D) 逻辑控制端 VIH 高电平 1.4 V VIL 逻辑控制端 0.4 V 低电平 CTRL一线脉冲 THI 1 12 us 高电平时间 CTRL一线脉冲 TLO 1 12 us 低电平时间 TOFF CTRL 关断时间 100 us AT Attack time VDD =3.6V, NCN 10 ms RL Release time VDD =3.6V, NCN 1.1 s AMAX 最大衰减增益 NCN -10 dB Nsiway
1 I. a | G. m00 FE 5C: G 0N20 ” I22 F ,G. 5 TR? i o " 'GF 1 ATEY Im 12 a GNU F IG. 6 US. Patent Fe0,1998 Sheetf15 5,717,962 FP UM TTL STON STOFF _ _ _ _ + 1 9 GA LIGHT k WAVEFORM FIG. 7 ll '1 < LMVE mM
Input Voltage(1) VIL1 -0,3 0,6 V (except OSC1) VIH1 2,2 VDD Input Voltage(2) VIL2 -0,2 1.0 V V DD-1.0 V V ( OSC1) IH2 DD Output Voltage (1) VOL1 0,4 I =1.2mA OL V (DB0 TO DB7) V OH1 2,4 OH=-0.205mA Output Voltage (2
u . Er w2rd für ein beliebiges Tastverhältnis V und Periodendauer T: T T = t1+ t2 t1 = V u = uSAT+t1 + uSAT−t2 = u SAT+t1+ u SAT−(T − t1) (7) M t + t T 1 2 Für die Aufladung des Kondensators im Zeitabschnitt t gilt: 1 −1 −1 u H RTCT ⎛ uH ⎞ τ u M + = u SAT+ + (uT −− u SAT+) e =
35/49 2008/08/18 ST7920 Built in voltage booster Voltage Doubler V Reference Voltage OUT Vss VD2 CAP1M Voltage Doubler Reference Voltage CAP1P VD2 CAP2M CAP2P CAP3M VSS VOUT VOUT External reset timing VDD Tres XRESET Trw XRESET pulse width Trw 10us RESET start time Tres 50ns www.DataSheet4U.com V4.0
mA (3) Power Supply CC + ICi Partial - 0.6 1.1 mA (4) Current Standby - 0.1 10 μA (5) Internal clock fFLM Normal display - (75) - Hz Frame mode operation Frequency Normal display RGB I/F mode fFLM (75)
mA (3) Power Supply CC + ICi Partial - 0.6 1.1 mA (4) Current Standby - 0.1 10 μA (5) Internal clock fFLM Normal display - (75) - Hz Frame mode operation Frequency Normal display RGB I/F mode fFLM (75)
is in this example 8us/DIV: All these error are as well when changing from 40k to 512k and from 51k to 1M. 49. Artifacts on display when sampling with 400MS/s. Set 40k and 4us/DIV: on the right part of the picture you can
is in this example 8us/DIV: All these error are as well when changing from 40k to 512k and from 51k to 1M. 49. Artifacts on display when sampling with 400MS/s. Set 40k and 4us/DIV: on the right part of the picture you can
0 0 1 S/C R/L X X changing DDRAM contentsisplay witho37us shift 0 0 0 0 1 DL N F X X Sets interface data length (DL) Function set Sets number of display lTnes (N) 37us Set CGRAM 0 0 0 1 ACG ACG ACG ACG ACG
0 0 1 S/C R/L X X changing DDRAM contentsisplay witho37us shift 0 0 0 0 1 DL N F X X Sets interface data length (DL) Function set Sets number of display lTnes (N) 37us Set CGRAM 0 0 0 1 ACG ACG ACG ACG ACG
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
Bild
