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Datei
icache.vhd
bit; variable b0Used : bit; begin if (reset_in_reset = '1') then read_state <= idle; read_addr <= (others => '0'); bufferIndex := 0; avalon_slave_readdata <= (others => '0'); avalon_slave_waitrequest <= '0'; clearValids; elsif (rising_edge(clock_in_clk)) then case read_state is when idle => if (avalon_slave_read
in „warum Registers Added for RAM Pass-Through Logic wenn kein gleichzeitiger Zugriff?“ · FPGA, VHDL & Co. ·
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Datei
icache.vhd
bit; variable b0Used : bit; begin if (reset_in_reset = '1') then read_state <= idle; read_addr <= (others => '0'); bufferIndex := 0; avalon_slave_readdata <= (others => '0'); avalon_slave_waitrequest <= '0'; clearValids; elsif (rising_edge(clock_in_clk)) then case read_state is when idle => if (avalon_slave_read
in „warum Registers Added for RAM Pass-Through Logic wenn kein gleichzeitiger Zugriff?“ · FPGA, VHDL & Co. ·
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Datei
UART_TX_8N1.vhd
; tick_counter <= (others=>'0'); tx<='0'; end if; if tick_counter=tick then tick_counter <= (others=>'0'); case state is when start => state <= data0; tx<=data_in(0); when data0 => state <= data1; tx<=data_in(1); when data1
in „Anfängerfrage: Übertragung starten“ · FPGA, VHDL & Co. ·
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Datei
regf.vhd
"11011" => D_OUT1 <= D_OUT; when "11100" => D_OUT1 <= D_OUT; when "11101" => D_OUT1 <= D_OUT; when "11110" => D_OUT1 <= D_OUT; when "11111" => D_OUT1 <= D_OUT; when others => D_OUT1 <= (others => 'U'); end case; end process read1;
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Datei
LVDS_TX.vhd
<= "10011111"; blu <= "11111001"; process (lvds_clk, rst) begin if (rst = '0') then tx0_sreg <= (others => '0'); tx1_sreg <= (others => '0'); tx2_sreg <= (others => '0'); tx3_sreg <= (others => '0'); tft_clk <= '0'; state <= s0; h_cnt <= 0; v_cnt <= 0; elsif (lvds_clk'event and lvds_clk='1') then --
in „LVDS seraliser“ · FPGA, VHDL & Co. ·
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Datei
ALU.vhd
Sel, CIn, Oa, Ob) Variable TempAdd : std_logic_vector(32 downto 0); begin --Default Werte = Y <= (Others => '0'); COut <= '0'; TempAdd := (Others => '0'); Z <= '0'; case Sel is when "0000" => Y <= Ob; when "0001" => TempAdd := Oa + Ob + CIn; Y <= TempAdd(31 downto 0); COut <= TempAdd(32); if TempAdd(31
in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·
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Datei
counter.vhd
std_logic_vector(31 downto 0); begin process(clk,enable,reset,switches,count) begin case switches is when "0001" => q <= count(7 downto 0); when "0010" => q <= count(15 downto 8); when "0100" => q <= count(23 downto 16); when "1000" => q <= count(31 downto 24); when others => q <= (others => 'Z'); --Tristate end case; if reset = '1' then --Asynchroner Reset q <= (others => '0'); count <= (others => '0'); elsif rising_edge(clk) then if enable = '0' then --Synchroner Zähler mit enable count <= count +1; end if; end if; end process; end Behavioral;
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Datei
x7seg_vhd.vhd
end process anode_selector; segment_mux : process begin wait until rising_edge(clk); anodes <= (others=>'0'); anodes(anode_cnt) <= '1'; case anode_cnt is when 0 => bcd_val<=dat(3 downto 0); when 1 => bcd_val<=dat(7 downto 4); when 2 => bcd_val<=dat(11 downto 8); when 3 => bcd_val<=dat(15 downto 12);
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Datei
Stickstoff.vhd
-750mbar when others => Wert_Druck_Vorwahl <="000000000000"; end case; -- Aufnahme Wert Feuchtevorwahl (sel0, sel1, sel2) -- LSB -> MSB case S5 is when "011" => Wert_Feuchte_Vorwahl <="000100101000"; --entspricht
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Datei
NEC_Decoder.vhd
; else state <= idle; end if; end if; when repeat => if (necsr = "11") then -- warten auf 1 --> erstes Bit cnt <= 0; if (cnt>rptlen) then -- Neue Übertragung state <= rx; bits <= (0=>'1', others=>'0'); else Repeated <= '1'; -- wiederholte Übertragung
in „counter vhdl“ · FPGA, VHDL & Co. ·
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Datei
sinus_574mhz.vhd
data4 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data5; when data5 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data6; when data6 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data7; when data7 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data8; when
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Datei
counter.txt
std_logic_vector (4 downto 0); begin if (DIR='1') then -- construction of a look-up-table for the next state when counting up case count is when "1001" => next_state<="0000"; when others => next_state<=count+1; end case; end if; if (DIR='0') then -- construction of a look-up-table for the next state when counting
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Datei
main.vhd
WAIT_STATE_2; null; when WAIT_STATE_2 => NEW_STATE <= WAIT_STATE_3; null; when WAIT_STATE_3 => NEW_STATE <= LATCH_DATA_STATE; null; when LATCH_DATA_STATE => NEW_STATE <= LATCH_ADDR_STATE; null; when others => NEW_STATE <= RESET_STATE
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Datei
main.vhd
signal read_bit :STD_LOGIC :='0'; begin P1:process(ASI_ASIC_IN_DUTY) begin case ASI_ASIC_IN_DUTY is when "01" => duty_cycle <=3300; when "10" => duty_cycle <=6600; when "11" => duty_cycle <=10000; when others => duty_cycle <=0; end case; end process P1; P2:process(CLK,reset) begin if (reset='1') then current_s
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Datei
main.vhd
signal read_bit :STD_LOGIC :='0'; begin P1:process(ASI_ASIC_IN_DUTY) begin case ASI_ASIC_IN_DUTY is when "01" => duty_cycle <=3300; when "10" => duty_cycle <=6600; when "11" => duty_cycle <=10000; when others => duty_cycle <=0; end case; end process P1; P2:process(CLK,reset) begin if (reset='1') then current_s
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Datei
mmb.vhd
011 512Kb SRAM CS_Latch <= "011"; if AVR_AH(7 downto 2) = "000001" then case AVR_AH(1 downto 0) is when "01" => CS_Latch <= "111"; when "10" => CS_Latch <= "110"; when "11" => CS_Latch <= "101"; when others => NULL; end case; end if; end if; end process; process(AVR_WR, AVR_RD, AVR_AD, CS_Latch, Bank_Register
in „AVR Ethernet Platine“ · Mikrocontroller und Digitale Elektronik ·
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Datei
prbs_checker.vhd
; -- Internal expected PRBS state and status signal expected : std_logic_vector(15 downto 0) := (others => '0'); signal sync_reg : std_logic := '0'; signal err_cnt : unsigned(31 downto 0) := (others => '0'); signal loss_cnt : unsigned(31 downto 0) := (others => '0'); -- Simple sync state machine: require
in „HW Link testen, auf datenintegrität, Frame loss“ · FPGA, VHDL & Co. ·
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Datei
Sinc_filt.vhd
std_logic_vector(diff3_tmp(DATA_BIT_SIZE-2 downto 0)); DataOut_scale(15-(DATA_BIT_SIZE-1) downto 0) <= (others=>'0'); -- with diff3(DATA_BIT_SIZE-1) select -- DataOut <= (others => '1') when '1', -- --diff3(DATA_BIT_SIZE-2 downto DATA_BIT_SIZE-17) -- std_logic_vector(diff3(DATA_BIT_SIZE-2 downto DATA_BIT_SIZE-17)) -- when others; end generate DataBitSize_lt16; end Behavioral;
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Datei
asm.vhd
<= S2; else next_state <= S1; end if; when S2 => product <= std_logic_vector(result); if M(0) = '1' then add <= '1'; end if; next_state <= S3; when S3 => product <= std_logic_vector(result_shift); shift <= '1'; CU <= '1'; if CD = '1' then next_state <= S4; product <= std_logic_vector(result); else next_state <= S2; end if; when S4 => done_int <= '1'; next_state <= S0; when others => next_state <= S0; end case; end process; end Behavioral;
in „Sequential System Design Using ASM Charts“ · FPGA, VHDL & Co. ·
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Datei
lauflicht_zaehler.vhd
' then temp := F0 & F1 & F2 & F3; case temp is when "1000" => if COUNTER(17) = '1' then if M_Bit = '0' then LED <= LED + 1; end if; M_Bit <= '1' ; else M_Bit <= '0' ; end if; when "0100" => if COUNTER(19) = '1' then if M_Bit = '0' then LED <= LED + 1
in „Addition & Multiplikation mit FPGA“ · FPGA, VHDL & Co. ·
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Datei
blitz_adress_decoder.txt
Adresse an Ausgangspins a7_0_out <= adr16_0(7 downto 0); a16_out <= adr16_0(16); cs_ram<='0' when adr16_0(16)='1' else '1'; cs_lcd<='0' when adr16_0=B"0" & X"FFFF" else '1'; cs_outport<='0' when adr16_0=B"0" & X"FFFE" else '1'; cs_inport<='0' when adr16_0=B"0" & X"FFFD" else '1'; cs_ctrl<='0' when
in „interne Chip-Select-Signale erzeugen“ · FPGA, VHDL & Co. ·
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Datei
blitz_adress_decoder.vhd
a7_0_out <= adr16_0(7 downto 0); a16_out <= adr16_0(16); end process; cs_ram<='0' when adr16_0(16)='1' else '1'; cs_lcd<='0' when adr16_0(16)='0' AND adr16_0(1 downto 0)=b"11" else '1'; cs_outport<='0' when adr16_0(16)='0' AND adr16_0(1 downto 0)=b"10" else '1'; cs_inport<='0' when adr16
in „interne Chip-Select-Signale erzeugen“ · FPGA, VHDL & Co. ·
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Datei
warenautomat.vhd
stored_items_next <= stored_items_reg; error_next <= error_reg; hex3_next <= hex3_reg; hex2 <= (others=>'1'); hex1_disp <= money_reg; -- there are only multiples of 10, so this sevensegment is always zero hex0_disp <= (others=>'0'); case state_reg is when idle => -- money input if (r_e_pb(0)='1') then
in „FSM - zu komplexes Ergebnis in Synthese“ · FPGA, VHDL & Co. ·
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Datei
tb_FIR_AD7960.vhd
std_logic := '1'; -- slave is ready signal s_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload -- Data master channel signals signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0')
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Datei
acc_sensor.vhd
count_global<=count_global+1; cs<='1'; dio_en<='1'; dio_signal<='0'; nullbit<='1'; ce_global<='0'; when 4 => resultout3<=result; count_confbits<=count_confbits+1; count_global<=count_global+1; cs<='1'; dio_en<='1'; dio_signal<='0'; nullbit<='1'; ce_global<='0'; newdata<='1'; when others => end case; when
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Datei
i2c_slave.vhd
if Reset_n='0' then state_q <= IDLE; error_q <= NO_ERROR; --transfer_q <= READ; rx_shiftreg_q <= (others=>'0'); tx_shiftreg_q <= (others=>'0'); rx_data <= (others=>'0'); wr_buf_q <= (others=>'0'); ld_tx_shiftreg_q <= false; ld_tx_2_q <= false; ld_tx_3_q <= false; busy_q <= false; tx_empty_q <= '0'; --
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Datei
sample2.vhd
_1; -- USB read byte 1 when wait_for_rxf_low_1 => if(nUSB_RXF_LCH = '0') then STATE_MACHINE <= usb_read_1; end if; when usb_read_1 => STATE_MACHINE <= wait_one_cycle_1; when wait_one_cycle_1 => STATE_MACHINE <= wait_for_rxf_low
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Datei
SDRAM_Controller.vhd
if; when init_LMR => current_state <= init_LMR1; sdram_cmd <= CMD_MRS; --sdram_addr <= (others => '0'); --sdram_addr(6 downto 4) <= std_logic_vector(to_unsigned(SDRAM_CAS, 3)); -- latency mode --sdram_addr(3
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Datei
SDRAM_Controller.vhd
if; when init_LMR => current_state <= init_LMR1; sdram_cmd <= CMD_MRS; --sdram_addr <= (others => '0'); --sdram_addr(6 downto 4) <= std_logic_vector(to_unsigned(SDRAM_CAS, 3)); -- latency mode --sdram_addr(3
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Datei
tuerAutomat.vhdl
CASE aktueller_zustand IS -- WHEN state_wait => timer <= timer + 1; -- IF timer = 6 THEN sechsSekFlag <= '1'; timer <= 0; --folge_zustand <= state_idle; sechsSekFlag <= '1'; -- ELSE sechsSekFlag <= '0'; -- END IF; -- WHEN OTHERS =>
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Datei
Counter.vhd
architecture body event_counter : process (clk, reset) begin if reset='0' then cnt <= 0; outputbuffer <= (others => '0'); state <= wait_for_count ; else if clk = '1' and clk'event then case state is when wait_for_count => if timebase ='0' then state <= door_closed ; else if count_int = '1' then state <= count_recognized
in „Event Counter funktioniert nur in der Simulation“ · FPGA, VHDL & Co. ·
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Datei
ATARI_PBI_FPGA.vhd
led1; -- 2. 8fach LED Leiste when 14 => segment7 <= led16 & led15 & led14 & led13 & led12 & led11 & led10 & led9; when others => mux_nibble <= (others => '0'); segment7 <= "00000000"; end case; end if; end process set_mux_nibble; --
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Datei
MMB.vhd
, AVR_AH) begin if AVR_WR = '0' and AVR_AH(7 downto 2) = "000100" then case AVR_AH(1 downto 0) is when "01" => Bank_Reg <= AVR_AD; -- 0x11?? when "10" => Port_Reg <= AVR_AD; -- 0x12?? when others => NULL; end case; end if; end process; process(AVR_RD, AVR_AH, Bank_Reg, Port_Reg) begin AVR_AD <= (others => 'Z'); if AVR_RD = '0' and AVR_AH(7 downto 2) = "000100" then case AVR_AH(1 downto 0) is when "01" => AVR_AD <= Bank_Reg; -- 0x11?? when "10" => AVR_AD <= Port_Reg; -- 0x12?? when others => NULL; end case; end if; end process; SPI_CS <= Port_Reg; SRAM_AH <= Bank_0 when A15 = '0' else Bank_1;
in „AVR Ethernet Platine“ · Mikrocontroller und Digitale Elektronik ·
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Datei
MMB.vhd
, AVR_AH) begin if AVR_WR = '0' and AVR_AH(7 downto 2) = "000100" then case AVR_AH(1 downto 0) is when "01" => Bank_Reg <= AVR_AD; -- 0x11?? when "10" => Port_Reg <= AVR_AD; -- 0x12?? when others => NULL; end case; end if; end process; process(AVR_RD, AVR_AH, Bank_Reg, Port_Reg) begin AVR_AD <= (others => 'Z'); if AVR_RD = '0' and AVR_AH(7 downto 2) = "000100" then case AVR_AH(1 downto 0) is when "01" => AVR_AD <= Bank_Reg; -- 0x11?? when "10" => AVR_AD <= Port_Reg; -- 0x12?? when others => NULL; end case; end if; end process; SPI_CS <= Port_Reg; SRAM_AH <= Bank_0 when A15 = '0' else Bank_1;
in „AVR Ethernet Platine“ · Mikrocontroller und Digitale Elektronik ·
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Datei
i2cmap.vhdl
ctrl.select_wdata <= '1'; when others => end case; -- READ else case addr is when R_I2C_Stat => data_out(B_RXTX_READY) <= stat.rxtx_ready; data_out(B_HOLD) <= stat.hold; data_out(B_NAK) <= stat.nak; data_out(B_BUSY) <= stat.busy;
in „Generieren von VHDL aus Gerätebeschreibungen“ · FPGA, VHDL & Co. ·
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Datei
uart.vhd
statussenden<=1; counter2:=0; txsenden:=txstartbuffer; txbusyser<='1'; else statussenden<=0; end if; end if; when others => null; end case; end if; --end if; else serout<='1'; counterout<=0; statussenden<=0; end if; end process seroutx; serstarten: process(txenable,txbusyser,reset) begin if reset='1' then if txbusyser
in „Verständnisprobleme synchron, asynchron“ · FPGA, VHDL & Co. ·
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Datei
LCD-Gesamt.txt
if; elsif (reset='1') then init_start<='0'; end if; end process; with state_lcd select lcd_rs<='1' when lcd6|lcd8|lcd10|lcd12|lcd14|lcd16|lcd18|lcd20|lcd22|lcd24|lcd26|lcd28|lcd30|lcd32|lcd34|lcd36, '0' when others; with init_start select MuxS<='0' when '1', '1' when others; with state_lcd select db<=
in „LCD Ansteuerung mit spartan-3E starter“ · FPGA, VHDL & Co. ·
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Datei
receive.vhd
Receive signal RxByteCounter : integer range 0 to 1521 := 0; signal Payload : byte(0 to 1507) := (others => "00000000"); signal RxCRC : std_logic_vector(31 downto 0) := (others => '1'); -- LED signal ledvec : std_logic_vector(15 downto 0) := (others => '0'); begin -- Generieren der Ethernet-Clock EthClk
in „Fehler beim Erkennen der Präambel (Ethernet)“ · FPGA, VHDL & Co. ·
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Datei
nibble_data.vhd
when x"8A3" => counter <= (others => '0'); busy <= '0'; -- -- MIT LOOP EINFÜGEN der Daten!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- when others => --data <= "0000"; -- if counter >= x"061" and counter
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Datei
MPMC_NPI.vhd
cnt_DataWordsPop : integer range 0 to 15 := 0; signal WR_Addr_int : std_logic_vector(31 downto 0) := (others => '0'); signal RD_Addr_int : std_logic_vector(31 downto 0) := (others => '0'); begin --- debug signals --- db_MPMC_RD_Addr <= (others => '0'); --- end debug signals --- RD_CLK <= MPMC_CLK0; WR_CLK
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PDF
xapp105_CPLD_VHDL_Introduction.pdf
010" when "00000100", "011" when "00001000", "100" when "00010000", "101" when "00100000", "110" when "01000000", "111" when "10000000", "XXX" when others; end architecture ARCH; In both cases, three macrocells
in „xilinx CPLD“ · FPGA, VHDL & Co. ·
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Datei
sram.vhd
then state<="000"; ramwe <= '1'; ram_io <= "ZZZZZZZZ"; elsif rising_edge(clk) then case state is when "000" => --ram_io<= (others => 'Z'); if we='1' then state<="001"; else state<="100"; end if; -- do<=ram_io; when "001" => ram_io<=di; ramwe <= '1'; ram_oe <= '1'; state <= "010"; when "010" => ramwe <='0'; ram_io<=di; state <="000"; when "100" => ramwe <= '1'; ram_oe <='0'; ram_io<= (others => 'Z'); state<="101"; when "101" => do<=ram_io; state <= "000"; when others => state <= "000"; end case; end if; end process; end Behavioral;
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Datei
bit.vhd
"1000"=>LED<="1001"; when"1001"=>LED<="1010"; when"1010"=>LED<="1011"; when"1011"=>LED<="1100"; when"1100"=>LED<="1101"; when"1101"=>LED<="1110"; when"1110"=>LED<="1111"; when"1111"=>LED<="0000"; when others=>null; end case;
in „4 Bit Zähler“ · FPGA, VHDL & Co. ·
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Datei
tasten.vhd.txt
", '1' when "0010000000", '1' when "0100000000", '1' when "1000000000", '0' when others; with EINSTELL select EINSTINT <= '0' when "0000", '1' when "0001", '1' when "0010", '1' when "0100", '1' when "1000", '0' when others; INTERRUPT <= TASTINT or EINSTINT; end VERHALTEN;
in „VHDL - Problem“ · FPGA, VHDL & Co. ·
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Datei
spi2in.vhd
bitcounter = Laenge --> alle Bits uebertragen signal rx_reg_c : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); --Cosinus Register signal rx_reg_s : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); --Sinus Register signal rx_reg_temp_c : std_logic_vector(Laenge-1 downto 0) := (others=>'0'); --Cosinus
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PDF
RGS15128128WR000.pdf
contains confidential and propNeither it nor the information containedherein shall be disclosed to others or duplicated or used for others without the express written consent of RiTdisplay. http://www.ritdisplay.com REVISION RECORD REV. REVISION DESCRIPTION REV. DATE REMARK X01 ■ INITIAL RELEASE 2008.
in „OLED Display mit SSD1327 Controller ansteuern“ · Mikrocontroller und Digitale Elektronik ·
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Datei
debounce_mit_tb.vhd
RTL of debounce is -- registers signal state0, state1, state2: std_logic_vector(7 downto 0) := (others => '0'); signal key_pressed_old: std_logic_vector(7 downto 0) := (others => '0'); signal key_pressed: std_logic_vector(7 downto 0) := (others => '0'); begin process(clk) begin if rising_edge(clk) then
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Datei
tb02cpu2.vhd
+ 1; adreg <= dataIn(5 downto 0); else adreg <= pc; end if; -- ALU / Data Path case states is when "010" => akku <= ("0" & akku(7 downto 0)) + ("0" & dataIn); -- add when "011" => akku(7 downto 0) <= akku(7 downto 0) nor dataIn; -- nor when "101" => akku(8) <= '0'; -- branch not taken, clear carry when others => null; -- instr. fetch, jcc taken (000), sta (001) end case; -- State machine if (states /= "000") then states <= "000"; -- fetch next opcode elsif (dataIn(7 downto 6) = "11" and akku(8)='1
in „VHDL Grundlagen mininal CPU auf Spartan 6“ · FPGA, VHDL & Co. ·
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Datei
lx9_FT245_0.vhd
lx9_FT245 is port( CLK: in std_logic; D: inout std_logic_vector(7 downto 0); RXF: in std_logic; --when high do not read TXE: in std_logic; --when high do not write RD: out std_logic; WR: out std_logic; SIWU: out std_logic; CLKOUT: in std_logic; OE: out std_logic; PWRSAV: out std_logic; ACBUS8: out std_logic
in „FPGA zum PC über USB, FX2 oder FT2232H?“ · FPGA, VHDL & Co. ·
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Datei
lx9_FT245_0.vhd
lx9_FT245 is port( CLK: in std_logic; D: inout std_logic_vector(7 downto 0); RXF: in std_logic; --when high do not read TXE: in std_logic; --when high do not write RD: out std_logic; WR: out std_logic; SIWU: out std_logic; CLKOUT: in std_logic; OE: out std_logic; PWRSAV: out std_logic; ACBUS8: out std_logic
in „FPGA zum PC über USB, FX2 oder FT2232H?“ · FPGA, VHDL & Co. ·