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Datei
Incremental_Encoder.vhd
when "0110" => up_down <= '0'; ce <= '0'; error <= '1'; -- Fehler when "0111" => up_down <= '1'; ce <= '1'; error <= '0'; -- vorwaerts when "1000" => up_down <= '1'; ce <= '1'; error <= '0'; -- vorwaerts
in „maximale Xilinx CPLD clock Frequenz“ · FPGA, VHDL & Co. ·
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Datei
fsm.vhd
<= '0'; count_int <= count_int; end if; when S1 => if ain = '1' then count_int <= count_int + 1; else count_int <= count_int; end if; when S2 => if ain = '1' then count_int <= count_int + 1; else count_int <= count_int; end if; when others =>
in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. ·
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Datei
square_by_gradient.vhd
: T_GRADIENT := (others => '0'); constant C_X_MAX : T_GRADIENT := (others => '1'); signal current_x_q : T_X := C_X_MIN; signal left_x_q : T_X := C_X_MIN; signal lowest_x, upmost_x : boolean; begin --calc gradient -- see good
in „Ein DSP - aber 2 Multiplikationen. David Copperfield?“ · FPGA, VHDL & Co. ·
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Datei
CTRL.vhd
FSMState <= ActivateDevice; When X"D" => Null; When X"E" => Null; When X"F" => Null; When Others => Null; end case; Bank_FF <= Bank; Adress_FF <= Adress; When NOP => DDR2_RAS <= '1'; DDR2_CAS <= '1'; DDR2_WE <= '1'; FSMState <= Idle
in „Xilinx: zwei identische Register generieren, ohne dass diese wegoptimiert werden“ · FPGA, VHDL & Co. ·
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Datei
generic_fsm.vhd
signal counter : unsigned(1 downto 0); begin process begin wait until rising_edge(clk); case state is when 0 => counter <= "11"; led <= (others => '1'); for i in 1 to NoStates loop if (taster(i) = '0') then led <= (others => '0'); led(i) <= '1'; state <= i; end if; end loop; bla: for i in 1 to NoStates generate when i => if (taster(i) = '1') then led <= (others => '1'); state <= NoStates + 1; end if; end generate bla; when NoStates + 1 => if (counter = "00") then state <= R; else counter <= counter - 1; end if;
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Datei
Projekt.txt
stateD; i<=0; else i<=i+1; end if; when stateD=> if(i=100000000) then state <= stateA; i<=0; else i<=i+1; end if; end case; end if; end process; with State select T <= '0' when stateA|stateC, '1' when others; end Behavioral; Component: State_Register
in „Ampelsteuerung, LED Frequenz ändern??“ · FPGA, VHDL & Co. ·
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Datei
Main.vhd
process(ZUSTAND, ANFORDERUNG_NS, ANFORDERUNG_HS, BLINK_S) begin -- Defaultzuweisungen OUTPUT <= (others => '0') after 5 ns; FOLGEZUSTAND <= ZUSTAND after 5 ns; ANFORDERUNG_HS_CLEAR <= '0' after 5 ns; ANFORDERUNG_NS_CLEAR <= '0' after 5 ns; case ZUSTAND is when INIT => OUTPUT <= "1111111111" after 5 ns; COUNTER_EN <= '1'; if COUNT = "01110" then FOLGEZUSTAND <= MODUS; COUNTER_EN <= '0'; end if; when MODUS => OUTPUT <= (others => '0') after 5 ns; if BLINK_S = '0' then FOLGEZUSTAND <= HS_GRUEN_NS_ROT after 5 ns; else FOLGEZUSTAND <= DAUER_GELB after 5 ns; end if; when DAUER_GELB => OUTPUT <= "0000010010
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Datei
i2s_in.vhd
then q2 <= q1; end if; end if; end process stage2; lrmux: process (lrck_in) begin case lrck_in is when '1' => left_enable <= '1'; right_enable <= '0'; when others => right_enable <= '1'; left_enable <= '0'; end case; end process lrmux; leftshift: process(sclk, nreset) begin if nreset = '0' then left_reg
in „von langsamer in schnellere taktdomain“ · FPGA, VHDL & Co. ·
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Datei
SPI.txt
bitcounter = Laenge --> alle Bits uebertragen signal tx_reg : std_logic_vector(Laenge-1 downto 0) := (others => '0'); signal rx_reg : std_logic_vector(Laenge-1 downto 0) := (others => '0'); --signal txsrslave : std_logic_vector(0 downto 0) := ("000000000000000"); signal EN_MEASbit : std_logic_vector(0 downto
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Datei
Textausgabe.txt
<= "10"; end if; when "11" => if ( number_data(0) = '1' ) then next_COLOR <= "10"; end if; when others => NULL; end case; end if; -- Display the Right Score if ((pixel >= "01000000") and (pixel <= "01000011" )) and ((line
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Datei
AudioInterface.vhd
reg_ready_f : out std_logic ); end component; signal s_delay : std_logic_vector(11 downto 0) := (others => '0'); signal s_filter_input_data_l_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filter_input_data_r_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filtered_output_data_l
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
top_gesamt.vhd
Adresse, 00 bei Einzelansteuerung 11 bei alle Kanäle gleich dac_input(17 downto 16) <= adr; case adr is when "00" => dac_input(15 downto 0) <= data0; when "01" => dac_input(15 downto 0) <= data1; when "10" => dac_input(15 downto 0) <= data2; when "11" => dac_input(15 downto 0) <= data3; when others => dac_input(15 downto 0) <= (others => '0'); end case; elsif rising_edge(clk) then dac_input <= dac_input(22 downto 0) & '0'; -- serielle Ausgabe end if; dac_sdi <= dac_input(23); -- Ausgabe auf Datenleitung end process; end Behavioral
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Datei
fsm_3process.vhd
; end if; end process; output_decode : process(state,ain,reset) begin yout <= '0'; case(state) is when S0 => if reset = '0' then if ain = '1' then yout <= '1'; else yout <= '0'; end if; end if; when S1 => yout <= '0'; when S2 => yout <= '0'; when others => yout <= '0'; end case; end process; count <=
in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. ·
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Datei
ddr.vhd
-------- when Precharge0 => ic.cmd <= CMD_PRECHARGE; ic.adr(10) <= '1'; -- Precharge all operation. iin.s <= Precharge0Wait; -- PRECHARGE command period tRP: 15ns when Precharge0Wait => if i.c = 1 then iin.c <= 0
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Datei
FIRFilter.vhd
- 1) of std_logic_vector(3 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator signal a_sop : ASOP := ( others => x"000000000000" ); type ACOEF is array (0 to NBTAP - 1) of std_logic_vector(0 to DSIZE - 1); signal a_coeff : ACOEF := ( others => x"0000" ); begin blk_mem_gen : blk_mem_gen_0 PORT MAP ( clka =>
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
i2s_data_interface.vhd
architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
Neues_Textdokument__6_.txt
SYNC <= '0'; end if; if (( bit_count >= 0) and (bit_count <= 15)) then --Slot0-Tag case bit_count is when 0 => AC97_SDATA_OUT <= '1'; when 1 => AC97_SDATA_OUT <= '1'; when 2 => AC97_SDATA_OUT <= '1'; when others => AC97_SDATA_OUT <= '0'; end case; elsif (( bit_count >= 16) and (bit_count <= 35)) then AC97
in „ISE-WebPack: iSim stoppt ungewollt die Simulation“ · FPGA, VHDL & Co. ·
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Datei
fifo_dc.vhd
i_wr_clk, i_reset) begin if i_reset = '1' then s_write_reset_done <= '0'; s_read_reset_done_sr <= (others => '0'); s_wp_bin_wcd <= (others => '0'); s_rp_gray_wcd <= (others => '0'); else if rising_edge(i_wr_clk) then s_write_reset_done <= '1'; s_read_reset_done_sr <= s_read_reset_done_sr(0) & s_read_reset_done
in „Xilinx Spartan 3 xc3s400 FIFO mit hoher Frequenz“ · FPGA, VHDL & Co. ·
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Datei
log_rom.vhd
"00000101" => dout <= "000001110"; when "00000110" => dout <= "000010001"; when "00000111" => dout <= "000010100"; when "00001000" => dout <= "000010111"; when "00001001" => dout <= "000011010"; when "00001010" => dout <= "000011100"; when
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Datei
UART.vhd
STD_LOGIC := '0'; BEGIN PROCESS (CLK) IS BEGIN IF RISING_EDGE(CLK) AND CE='1' THEN CASE RX_BIT_COUNT IS WHEN 0 => IF(RX='0')THEN RX_BIT_COUNT <= 1; END IF; WHEN 9 => RX_BIT_COUNT <= 0; OUTP <= OUT_BUF; WHEN OTHERS => RX_BIT_COUNT <= RX_BIT_COUNT + 1; OUT_BUF <= RX & OUT_BUF(7 downto 1); END CASE; END IF; END PROCESS; PROCESS (CLK) IS BEGIN IF RISING_EDGE(CLK) AND CE='1' THEN CASE TX_BIT_COUNT IS WHEN 0 => IF(SEND_BUF='0' AND SEND='1')THEN TX_BIT_COUNT <= 1; TX <= '0'; ELSE TX <= '1'; END IF; SEND_BUF <= SEND; WHEN 9 => TX <= '1'; TX_BIT_COUNT <= 0; WHEN OTHERS => TX <= DATA(TX_BIT_COUNT-1); TX_BIT_COUNT
in „Arbeiten mit RS 232“ · Mikrocontroller und Digitale Elektronik ·
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Datei
i2s_data_interface.vhd
architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
i2s_data_interface.vhd
architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
i2s_data_interface.vhd
architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
i2s_data_interface.vhd
architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
mii_inout.vhd
= '1' then rxstate <= idle; rx_buffer <= (others => '0'); elsif rising_edge(clk100) and (rxclk_sync = '0') then rx_stb_o <= '0'; frame_start <= '0'; case rxstate is when idle => if rxdv = '1' then rxstate <= wa; rx_buffer <= (others => '0'); end if; when wa => rxstate <= data_lo; when data_lo => frame_start <= '1'; if rxdv = '0' then rxstate <= idle; else rx_buffer(7 downto 4) <= rxd; rxstate <= data_hi; end if; when data_hi => frame_start <= '1'; if
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Datei
counter.txt
std_logic_vector (3 downto 0); begin if (DIR='1') then -- construction of a look-up-table for the next state when counting up case count is when "1001" => next_state<="0000"; when others => next_state<=count+1; end case; end if; if (DIR='0') then -- construction of a look-up-table for the next state when counting down case count is when "0000" => next_state<="1001"; when others => next_state<=count-1; end case; end if; if ((RESET and DIR)='1') then -- Reset has the first priority count:="0000"; elsif (RESET='1' and DIR='0') then count
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Datei
i2c_slave_model.vhd
= 'd'; when "1110" => result := 'e'; when "1111" => result := 'f'; when others => result := 'x'; end case; return result; end; -- converts slv byte to two char hex-string function slv8_xstr (inp: STD_LOGIC_VECTOR
in „Probleme bei Lattice I2C EFB mit Wishbone Interface“ · FPGA, VHDL & Co. ·
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PDF
einf__hrung_in_vhdl.pdf
Auswahlwer- te nicht den kompletten Wertebereich ab, so muß in der letzten Alternative der Auswahlwert others verwendet werden, der alle noch nicht aufgeführten Auswahlwerte beinhaltet. Beispiel: case Kalendertag is -- Wertebereich von Kalendertag sei 1 bis 31 when 1 | 16 => Anweisungen für 1 und 16 ; when 2 => Anweisungen für 2 ; when 7 to 15 => Anweisungen für 7 bis 15 ; when others => Anweisungen für 3 bis 6 und 17 bis 31 ; end case; 2.4.4 Loop Anweisung in VHDL lassen sich unendliche Schleifen, sogenannte While-Schleifen und sogenannte
in „Erste Schritte mit FPGA - ich komme nicht weiter“ · FPGA, VHDL & Co. ·
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Datei
prog.txt
others => Wert_Druck_Vorwahl<="000000000000"; end case; -- Aufnahme Wert Feuchtevorwahl case S5 is when "001" => Wert_Feuchte_Vorwahl<="000000000010"; when "010" => Wert_Feuchte_Vorwahl<="000000000100"; when "011" => Wert_Feuchte_Vorwahl<="000000001000"; when "100" => Wert_Feuchte_Vorwahl<="000000010000"; when others => Wert_Feuchte_Vorwahl<="111111111111"; end case; ----------------------------------------------------------------------------------------
in „Betriebsblind“ · FPGA, VHDL & Co. ·
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PDF
INR-18650.pdf
test 9.2 External short-circuit test 9.3 Reverse charge test 9.4 Heating test 10.0. Warranty 11.0. Others 11.1 Storage for a long time 11.2 Others 12.0. Packing Proper use and handling of lithium ion cells Handling precaution and prohibitions of lithium Ion rechargeable cells and batteries Samsung SDI
in „LIOH austauschbar ?“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
SAMSUNG_INR18650-25R.pdf
test 9.2 External short-circuit test 9.3 Reverse charge test 9.4 Heating test 10.0. Warranty 11.0. Others 11.1 Storage for a long time 11.2 Others 12.0. Packing Proper use and handling of lithium ion cells Handling precaution and prohibitions of lithium Ion rechargeable cells and batteries Samsung SDI
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Datei
uart_tx.vhd
architecture RTL of uart_tx is signal enable : std_logic := '0'; signal txbaud : unsigned(19 downto 0) := (others => '0'); signal txdata : std_logic_vector(9 downto 0) := "1000000000"; signal tick : std_logic := '0'; signal tickcnt : unsigned(19 downto 0) := (others => '0'); signal bitcnt : integer range 0 to
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Datei
data_receiver.vhd
= '1'; when "111" => rx_filt <= '1'; when others => null; end case; end process; -- bit timing counter process(clk) begin if rising_edge(clk) then if ce='1' then if rx_smp(2 downto 1) = "10" and state=idle then
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Datei
wb_sm_async_bridge.vhd
s_exit_without_ack <= false; wb_cyc_o <= '0'; wb_stb_o <= '0'; s_dsp_ardy <= '0'; wb_we_o <= '0'; wb_sel_o <= (others => '1'); wb_dat_o <= (others => '0'); else case s_wb_bridge_states is when wait_for_dsp_access_state => s_dsp_ardy <= '0'; if s_dsp_ams_n_sync = '0' then -- active memory select from dsp wb_adr_o <
in „Hilfe bei timing constraints für asynchrones Interface zu Blackfin DSP“ · FPGA, VHDL & Co. ·
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Datei
TLC.txt
stateD; i<=0; else i<=i+1; end if; when stateD=> if(i=100000000) then state <= stateA; i<=0; else i<=i+1; end if; end case; end if; end process; with State select T <= '0' when stateA|stateC, '1' when others; end Behavioral; #############
in „Trafic-Lights-Controller, Clk Problem“ · FPGA, VHDL & Co. ·
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Datei
i2c_low.vhd
Send + Receive Ack data_int <= DATA; i2c_state <= ST_I2C_SEND_A; when "10" => -- I2C STOP i2c_state <= ST_I2C_STOP_A; when others => BUSY <= '0'; end case; end if; when ST_I2C_START_A => i2c_state <= ST_I2C_START_B; delay_flag <= '1'; delay_time <= DELAY_BIT; when ST_I2C_START_B
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Datei
sDFT.vhd
<= '1'; -- update FiFo with new sample from ADC state <= load_st; else state <= wait_st; end if; when load_st => x_diff <= resize(signed(f_din) - x_0, x_diff'length); -- load twfarr from Twiddle_ROM (implicitely) r_rden <= '1'; -- read Xk_old from FBin_RAM state <= calc_st; when calc_st => for i in
in „gh_fifo_sync_sr: loadless signals?“ · FPGA, VHDL & Co. ·
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Datei
ALU.vhd
Sel, ERG_SUMME, ERG_AND, ERG_OR, ERG_RSHIFT, ERG_MULT) begin Cout <= '0'; case Sel is -- Addieren when "0001" => Y <= ERG_SUMME(31 downto 0); COut <= ERG_SUMME(32); -- Subtrahieren = Addieren mit gesetztem Carry! -- Wir brauchen dafür kein Extra Opcode --Multiplizieren when "0011" => Y <= ERG_MULT(31 downto 0); -- AND when "0100" => Y <= ERG_AND; -- OR when "0101" => Y <= ERG_OR; -- Rechtschift when "0111" => Y <= '0'&ERG_RSHIFT; -- Unbekannter Opcode = Ergebnis undefiniert when others => Y <= (others => '-'); end case
in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·
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Datei
DUAL2BCD.vhd
zaehler: std_logic_vector(3 downto 0); begin process (RESET, CLK) begin if RESET = '1' then z <= (others => '0'); DECIMAL <= (others => '0'); READY <= '0'; zaehler <= "0000"; current_state <= start_state; elsif CLK'event and CLK = '1' then case current_state is when start_state => if START = '1' then
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Datei
serdec.vhdl
bitcnt<thr then data_serialized<='0'; bitcnt <= bitcnt+1; else -- bitcnt>=thr txbit<='1'; bitcnt<=(others=>'0'); data_serialized<='1'; end if; end if; end if; end process; advancestate: process (clk, state, data_serialized, writecommand, data_in) begin case state is when WAITFORDATA => if writecommand='1' then nextstate <= READDATA; end if; when READDATA => if data_in='1' then nextstate <= SERIALIZEDATA; end if; when SERIALIZEDATA => if data_serialized='1' then nextstate <= WAITFORDATA; end if; end case; if (state=READDATA or state=SERIALIZEDATA
in „Anfängerproblem: Prozess einmal ablaufen lassen“ · FPGA, VHDL & Co. ·
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Datei
main.vhd
= 27; -- long wait -- when x"a" => next_state <= 1; -- error -- error <= '1'; when others => next_state <= 40; -- error error <= '1'; -- if addr = new_addr then -- new_addr <= new_addr + 1; -- addresse einen runter -- end if;
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Datei
adau1761_configuraiton_data.vhd
"; when "0000011000" => data <= "101000000"; when "0000011001" => data <= "100010101"; when "0000011010" => data <= "100000001"; when "0000011011" => data <= "011111111"; when "0000011100" => data <= "101110110
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
Kaffeeautomat.vhd
(others => '0'); begin -- Einsynchronisieren Pr50Csr <= Pr50Csr(3 downto 0)&Pruefer50Cent when rising_edge(clk); Pr1Esr <= Pr1Esr(3 downto 0) &Pruefer1Euro when rising_edge(clk); Pr2Esr <= Pr2Esr(3 downto 0) &Pruefer2Euro when rising_edge(clk); -- Flankenerkennung Pr50C <= '1' when Pr50Csr(4 downto 1) = "0111" else '0'; Pr1E <= '1' when Pr1Esr(4 downto 1) = "0111" else '0'; Pr2E <= '1' when Pr2Esr(4 downto 1) = "0111" else
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Datei
FIFO.vhd
write to FIFO -- push : set to 1 for 1 clk to write 1 data word to FIFO -- push must not be applied when "full" is true -- full flag: goes high when FIFO got full with last push -- overflow flag : goes high when a push occurs while "full" flag is set -- can only be reset by applying "reset" -- -- read
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Datei
top.vhd
<= "0000"; m_axis_video_tid <= "0"; m_axis_video_tdest <= "0"; -- state <= STREAM_BEREIT; end if; when others => state <= STREAM_BEREIT; --m_axis_video_tvalid <= '0'; end case; end if; end if; end process; -- Auf den Simulationsausgang das gleiche legen wie auf den VFIFO (wird später auskommentiert)
in „MIG mit AXI4 Interfacenauf Spartan 6“ · FPGA, VHDL & Co. ·
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PDF
IFR14500EC-600mAh.pdf
Model: IFR14500EC-600mAh 4 3. Specification 4 4. Battery Cell Performance Criteria 5 5. Storage and Others 7 6. Battery Cell Drawing (all unit in mm, not in scale) 7 Handling Precautions and Guideline 8 1. Charging 8 2. Discharging 8 3. Protection Circuit Module (PCM) 9 4. Storage 9 5. Others 9 Customer
in „Externer Akku an digitales Heizkörperthermostat“ · Mikrocontroller und Digitale Elektronik ·
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Datei
SOB.vhd
ReadyxSO <= std_logic_vector(to_unsigned(cnt,3)); -- end process FIR_comb ; -- ReadyxSO <= "000" when DataBufxD="0000" else -- "001" when DataBufxD="0001" or DataBufxD="0010" or DataBufxD="0100" or DataBufxD="1000" else -- "010" when DataBufxD="0011" or DataBufxD="0110" or DataBufxD="1100" or DataBufxD
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Datei
bubble.vhd
=> '0'); signal addrb_d3 : std_logic_vector(5 downto 0) := (others => '0'); signal addrb_d4 : std_logic_vector(5 downto 0) := (others => '0'); signal dout_a : std_logic_vector(15 downto 0) := (others => '0'); signal din_a : std_logic_vector(15 downto 0) := (others
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Datei
AudioInterface.vhd
std_logic; CLK_OUT : out std_logic ); end component; signal s_delay : std_logic_vector(11 downto 0) := (others => '0'); signal s_filter_input_data_l_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filter_input_data_r_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filtered_output_data_l
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
sigmadelta.vhd
end process; -- Erzeugen des D-FlipFlop zum Zwischenspeichern -- with clk select dIn_alt <= dIn_neu when '1', dIn_alt when others; Komperator: process (dIn_alt) -- Herausfiltern des MSBit -- begin alt_conv <= std_logic_vector(din_alt); dOut_read <= alt_conv (10); end process Komperator; Erzeugen: process (dOut_read) -- Erzeugen eines Vektors-- begin case dOut_read is when '0' => dOutm <= "0000000000"; when '1' => dOutm <= "1111111111"; when others => dOutm <= "0000000000"; end case; dOutm_conv <= signed (dOutm); end process Erzeugen; data_out <= dOut_read; -- Ausgeben
in „Problem bei der Simulation (Buskonflikt)“ · FPGA, VHDL & Co. ·