1 | void init_Clock( void )
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2 | { unsigned char i = 0;
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3 | // Turning XT1 (32kHz) on
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4 | _BIC_SR (OSCOFF); // Turn on XT1
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5 | BCSCTL1 &= ~XTS; // LF mode
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6 | for (i = 0xFFFF; i > 0; i--); // Time for osc. to set
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7 | // XT1 is on
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8 |
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9 | // Turning XT2 (8MHz) on
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10 | BCSCTL1 &= ~XT2OFF; // Turn on XT2
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11 | do
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12 | { // pruefroutine, ob 8 Mhz-oszillator schon stabil ist
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13 | IFG1 &= ~OFIFG; // OSCFault flag loeschen (zeigt oszillatorfehler an)
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14 | for (i=0xFF;i>0;i--); // warten, ob es wieder gesetzt wird
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15 | }
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16 | while ((IFG1 & OFIFG) != 0); // OSCFault immer noch gesetzt?
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17 |
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18 | BCSCTL2 |= SELM_2 + DIVM_0 + // MCLK source is XT2, MCLK div is 1
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19 | SELS + DIVS_0; // SMCLK souce is DCO, SMCLK div is 1
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20 | BCSCTL1 |= DIVA_0; // Divider for ACLK is 1
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21 |
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22 | // At this point we have the following clock configuration:
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23 | // MCLK is 8 MHz (from XT2)
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24 | // SMCLK is 8 MHz (from XT2)
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25 | // ACLK is 32 kHz (from XT1)
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26 | }
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27 |
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28 | void main(void)
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29 | {
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30 | _STOP_WATCHDOG(); //definiert in "msp430def.h"
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31 |
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32 | ptr_mw = &mw;
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33 | ptr_mw0 = &mw0;
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34 | ptr_mw1 = &mw1;
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35 | ptr_mw2 = &mw2;
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36 |
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37 | P1SEL = 0x00; //Std.IO
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38 | P1DIR = 0xFF; //alles Ausgänge
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39 |
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40 | P2SEL = 0x00; //Std.IO
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41 | P2DIR = 0xFF; //alles Ausgänge
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42 |
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43 | P3SEL = 0xf0; //P3.0..3 Standard I/O; P3.4..7 Peripheral Modul Function (UART)
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44 | P3DIR = 0x00; //P3.0..3 Ausgaenge; P3.4..7 = x
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45 |
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46 | P6SEL = 0xFF; //Peripheral Modul Function (ADC12)
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47 |
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48 | //init_Clock();
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49 | timera_init();
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50 | timerb_init();
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51 | init_DAC();
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52 | init_ADC();
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53 | init_SIO();
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54 |
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55 |
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56 | //Interruptfreigaben
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57 | //ADC12IE = 0xFFFF; //Int-Freigabe für das Ergebnisregister ADC12MEM0
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58 | //ADC12IE = ADC12IE2;
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59 | ADC12IE = 0x0004; // ADC12 memory 0,2,
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60 | //ADC12IE = 0x0001;
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61 | TACCTL0 |= CCIE; //Timer A C/C Int Enable (für TACCR0)
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62 |
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63 | TBCCTL0 |= CCIE; //Tiemr_B C/C Int Enable (für TBCCR0)
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64 |
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65 | IE1 |= UTXIE0; //SIO0 TX-Int freigeben
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66 |
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67 | _BIS_SR(GIE); //GIE = 1, globale Interruptfreigabe
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68 |
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69 |
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70 | TACTL |= MC_1; //Timer_A starten
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71 | // CPU Takt
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72 | DCOCTL = DCO0 + DCO1 + DCO2;
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73 | BCSCTL1 = RSEL0 + RSEL1 + RSEL2;
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74 | BCSCTL2 = SELM_0 + DIVM_0 + DIVS_0;
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75 |
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76 |
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77 | while(1); //Endlosschleife - Warten auf Interrupts
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78 |
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79 | }
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80 | void init_SIO(void)
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81 | {
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82 | //SIO0
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83 | ME1 |= UTXE0; //Transmitter enablen
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84 | U0CTL |= CHAR; //8 data bits, 1 stop bit, no parity (8N1)
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85 | //U0TCTL |= 0x10; //ACLK als UCLK festlegen
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86 | UTCTL0 |= SSEL1; // SMCLK als UCLK festlegen
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87 | //U0BR0 = 0x03; //9600 baud aus 32.768 kHz erzeugen
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88 | //U0MCTL = 0x4A; //Korrektur der Division (Tabelle auf 13-16)
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89 | //U0BR0 = 0x41; // 19200 baud aus 8 MHz erzeugen
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90 | //U0BR1 = 0x03; // siehe application note tabelle 1, seite 9
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91 | //U0MCTL = 0x09; // keine korrektur der division noetig
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92 | //UBR00=0xA0; UBR10=0x01; UMCTL0=0x00; /* uart0 8000000Hz 19198bps */
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93 | //UBR00=0x41; UBR10=0x03; UMCTL0=0x09; /* uart0 8000000Hz 9600bps */
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94 | UBR00=0x45; UBR10=0x00; UMCTL0=0xAA; /* uart0 8000000Hz 115107bp */
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95 | U0BR1 = 0x00;
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96 | U0CTL &= ~SWRST; //USART freigeben
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97 | // IFG1 &= ~UTXIFG0; //initales Int-Flag löschen
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98 | }
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