Hallo an alle,
erstmal, ich bin VHDL bzw. FPGA Anfänger, konnte jedoch meine ersten
erfolge am Demoboard schon verbuchen (Lauflichter, 7 Segment Anzeige,
Zustandsautomaten,...).
Jetzt versuche ich gerade einen einfachen I2C-Master zu beschreiben, der
nur senden kann. Dazu habe ich jede I2C Aktion (Start, Sende Bit, Lese
Ack, Stop) einzeln beschrieben. Diese Kommandos werden von einem höheren
Modul dann in der richtigen Abfolge gestartet.
Angehängt habe ich meinen VHDL-Source Code.
Dabei bekomme ich mehrere Warnungen, die mir zu denken geben:
1 | Warning (10631): VHDL Process Statement warning at i2c_low.vhd(225): inferring latch(es) for signal
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2 | or variable "SDA", which holds its previous value in one or more paths through the process
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3 |
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4 | Warning (10631): VHDL Process Statement warning at i2c_low.vhd(225): inferring latch(es) for signal
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5 | or variable "SCL", which holds its previous value in one or more paths through the process
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6 | Warning: Timing Analysis is analyzing one or more combinational loops as latches
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7 | Warning: Node "I2C_LOW:I2C|SDA_370" is a latch
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8 | Warning: Node "I2C_LOW:I2C|SDA$latch" is a latch
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9 | Warning: Node "I2C_LOW:I2C|SCL$latch" is a latch
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10 | Warning: Node "I2C_LOW:I2C|SCL_353" is a latch
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Mir ist klar, dass für SCL und SDA Latches erzeugt werden, da nicht in
jedem Zustand die beiden Leitungen geändert werden. Erkenne ich das
richtig?
Doch woher kommt die Kombinatorische Schleife??
1 | Warning: Found 14 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s)
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2 | analyzed as buffer(s) resulting in clock skew
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3 | Info: Detected gated clock "I2C_LOW:I2C|SCL~1" as buffer
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4 | Info: Detected gated clock "I2C_LOW:I2C|SCL~0" as buffer
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5 | Info: Detected gated clock "I2C_LOW:I2C|SDA~1" as buffer
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6 | Info: Detected gated clock "I2C_LOW:I2C|SDA~2" as buffer
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7 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_ACK_A" as buffer
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8 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_ACK_B" as buffer
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9 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_ACK_C" as buffer
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10 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_ACK_D" as buffer
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11 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_SEND_A" as buffer
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12 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_ACK_E" as buffer
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13 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_SEND_B" as buffer
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14 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_IDLE" as buffer
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15 | Info: Detected ripple clock "I2C_LOW:I2C|i2c_state.ST_I2C_SEND_C" as buffer
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16 | Info: Detected ripple clock "I2C_LOW:I2C|delay_flag" as buffer
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17 |
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18 | Warning: Can't achieve minimum setup and hold requirement CLOCK_24[0] along 8 path(s).
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19 | See Report window for details.
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Diese Warnungen verstehe ich leider (noch) nicht. Kann mir jemand dazu
Tipps geben?
Bitte gebt mir auch Kritiken zu meinem VHDL Code. Bin noch Anfänger und
kann Tipps gut gebrauchen ;)
Danke im Voraus!
lg Robert